IP Library › Granted Patent US 12,389,538
Granted Patent B2
US 12,389,538 · App. 18/159,930 · Granted Aug 12, 2025

Varying diameters of power-vias in a PCB based on via location

Inventor: Brian Mark Hostetler (Chippewa Falls, WI)
Assignee: Hewlett Packard Enterprise Development LP
H05K1/115H05K1/0218H05K3/4038H05K2201/093H05K2201/09636H05K2201/10818H05K2201/10984
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Quick Facts
Patent No.
US 12,389,538
App. No.
18/159,930
Granted
Aug 12, 2025
Kind
B2
Abstract

An electronic device may comprise a printed circuit board (PCB) and a power source and processing circuitry mounted to the PCB. The PCB comprises one or more power planes and a plurality of power vias electrically connected to the power planes. The power sources are electrically connected to the power planes. The processing circuitry is electrically connected to the plurality of power vias through a plurality of interconnects. Respective diameters of the plurality of power vias vary based on location.

Claims (36)

1. An electronic device comprising:

a printed circuit board (PCB) comprising a power plane and a plurality of power vias electrically connected to the power plane;

a power source mounted to the PCB and electrically connected to the power plane; and

an electronic component mounted to the PCB and electrically connected to the plurality of power vias through a plurality of interconnects;

wherein respective diameters of the plurality of power vias vary based on location;

wherein the respective diameters of the plurality of power vias vary based on distances of the power vias from a reference point;

wherein the electronic component comprises contact pads arranged in a pattern and electrically connected to the plurality of power vias by solder balls;

wherein the reference point corresponds to a center of the pattern of the contact pads; and

wherein the respective diameters of the plurality of power vias decrease as distances of the power vias from the center increase.

2. The electronic device of claim 1 ,

wherein the plurality of power vias are arranged in a plurality of zones concentrically nested around the reference point, each of the zones having a subset of the plurality of power vias, and

wherein, for each of the zones, the power vias in the respective zone have diameters that are the same as one another and different from the power vias in the other zones.

3. The electronic device of claim 1 ,

wherein the respective diameters of the plurality of power vias vary between 0.201 mm and 0.610 mm.

4. The electronic device of claim 1 ,

wherein the electronic component comprises processing circuitry.

5. The electronic device of claim 4 ,

wherein the processing circuitry comprises an application-specific-integrated-circuit.

6. The electronic device of claim 1 , further comprising:

a plurality of power sources, the power source being one of the plurality of power sources;

wherein the respective diameters of the plurality of power vias increase as distances of the power vias from one of the plurality of power sources increase.

7. An electronic device comprising:

a printed circuit board (PCB) comprising a power plane and a plurality of power vias electrically connected to the power plane;

a power source mounted to the PCB and electrically connected to the power plane; and

an electronic component mounted to the PCB and electrically connected to the plurality of power vias;

wherein the plurality of power vias are arranged in a plurality of zones comprising a first zone and a second zone, and

wherein the power vias in the first zone each have a first diameter and the power vias in the second zone each have a second diameter,

wherein the electronic component comprises contact pads arranged in a pattern and electrically connected to the plurality of power vias by solder balls,

wherein the plurality of zones are concentrically nested around the center of the pattern, and

wherein, for each of the plurality of zones, the diameters of the power vias in the respective zone are smaller than the diameters of the power vias in any of the zones closer to the center of the pattern and larger than the diameters of the power vias in any of the zones farther from the center of the pattern.

8. The electronic device of claim 7 ,

wherein the respective diameters of the plurality of power vias vary between 0.201 mm and 0.610 mm.

9. The electronic device of claim 7 ,

wherein the electronic component comprises processing circuitry.

10. The electronic device of claim 9 ,

wherein the processing circuitry comprises an application-specific-integrated-circuit.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 26, 2023
From: HOSTETLER, BRIAN MARK
To: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP
Reel/Frame 062498/0554 →
Continuity (1)
Related Publication 20240260188A1 · Aug 1, 2024
References Cited (26)
US 8907496B1 · Ning et al. · 2014 [cited by applicant]
US 10347592B2 · Stone · 2019 [cited by applicant]
US 10867916B2 · Biswas et al. · 2020 [cited by applicant]
US 11336167B1 · Vinciarelli · 2022 [cited by examiner]
US 20050098886A1 · Pendse · 2005 [cited by examiner]
US 20050146017A1 · Koide · 2005 [cited by examiner]
US 20100289596A1 · Makino · 2010 [cited by examiner]
US 20110074047A1 · Pendse · 2011 [cited by examiner]
US 20120068322A1 · Hanabe · 2012 [cited by examiner]
US 20140268586A1 · Hoshi · 2014 [cited by examiner]
US 20150054155A1 · Ohara · 2015 [cited by examiner]
US 20170311471A1 · Mao · 2017 [cited by examiner]
US 20180168039A1 · Numagi · 2018 [cited by examiner]
US 20180184514A1 · Yamada · 2018 [cited by examiner]
US 20180197801A1 · Naruse · 2018 [cited by examiner]
US 20200411494A1 · Hovis · 2020 [cited by examiner]
US 20200411495A1 · Hovis · 2020 [cited by examiner]
US 20210050318A1 · Marquart · 2021 [cited by examiner]
US 20210193567A1 · Cheah · 2021 [cited by examiner]
US 20210407948A1 · Kim · 2021 [cited by examiner]
US 20220139874A1 · Lee · 2022 [cited by examiner]
US 20220272834A1 · Westwood · 2022 [cited by examiner]
US 20240006286A1 · Sain · 2024 [cited by examiner]
US 20240006324A1 · Cheah · 2024 [cited by examiner]
US 20240021560A1 · Yeh · 2024 [cited by examiner]
Hughes, M., “Which Via Should I Choose? A Guide to Vias in PCB Design,” available online at <https://www.allaboutcircuits.com/technical-articles/which-via-should-i-choose-a-guide-to-vias-in-pcb-design/>, Nov. 7, 2018, 1… [cited by applicant]