Cross-point magnetoresistive memory array including self-aligned dielectric spacers and method of making thereof
Selector material layers are formed over the first electrically conductive lines, and magnetic tunnel junction material layers are formed over the selector material layers. The magnetic tunnel junction material layers are patterned into a two-dimensional array of magnetic tunnel junction (MTJ) pillar structures. A dielectric spacer material layer is deposited over the two-dimensional array of MTJ pillar structures. The dielectric spacer material layer and the selector material layers are anisotropically etched. Patterned portions of the selector material layers include a two-dimensional array of selector-containing pillar structures. Second electrically conductive lines are formed over the two-dimensional array of MTJ pillar structures.
1. A memory array, comprising:
first electrically conductive lines laterally extending along a first horizontal direction and laterally spaced apart from each other along a second horizontal direction;
a two-dimensional array of selector-containing pillar structures located over the first electrically conductive lines and including a respective selector element;
a two-dimensional array of magnetic tunnel junction (MTJ) pillar structures located over the two-dimensional array of selector-containing pillar structures and including a respective magnetic tunnel junction (MTJ);
a two-dimensional array of tubular dielectric spacers laterally surrounding the two-dimensional array of MTJ pillar structures and having a respective outer sidewall having a bottom periphery that coincides with a top periphery of a sidewall of a respective underlying one of the selector-containing pillar structures; and
second electrically conductive lines laterally extending along the second horizontal direction and overlying the two-dimensional array of MTJ pillar structures;
wherein each selector-containing pillar structure of the two-dimensional array of selector-containing pillar structures comprises a vertical stack including a lower selector electrode, a non-Ohmic selector material plate overlying the lower selector electrode, and an upper selector electrode overlying the non-Ohmic selector material plate; and
wherein the upper selector electrode within each selector-containing pillar structure comprises:
a base portion having a first cylindrical surface segment, wherein a bottom periphery of the first cylindrical surface segment coincides with a periphery of a top surface of the non-Ohmic selector material plate; and
a pedestal portion overlying the base portion and having a second cylindrical surface segment that is laterally offset inward from a cylindrical vertical plane including the first cylindrical surface segment.
2. The memory device of claim 1 , wherein a bottom periphery of the second cylindrical surface segment is adjoined to an inner periphery of an annular top surface of the base portion.
3. The memory device of claim 2 , wherein an outer periphery of the annular top surface of the base portion is adjoined to a top periphery of the first cylindrical surface segment.
4. The memory device of claim 1 , wherein the second cylindrical surface segment is laterally offset inward from the cylindrical vertical plane including the first cylindrical surface segment by a uniform lateral offset distance that equals a lateral thickness of each tubular dielectric spacer of the two-dimensional array of tubular dielectric spacers.
5. The memory device of claim 1 , wherein:
the second cylindrical surface segment is in contact with a portion of an inner sidewall of a respective one of the tubular dielectric spacers; and
the base portion comprises an annular top surface contacting an annular bottom surface of the respective one of the tubular dielectric spacers.