Techniques for MRAM MTJ top electrode connection
Some embodiments relate to an integrated chip having a memory cell overlying a substrate and comprising a top electrode. A top electrode via overlies the top electrode. A width of an upper surface of the top electrode via is greater than a width of an upper surface of the top electrode. A conductive via overlies the top electrode via. A width of an upper surface of the conductive via is greater than the width of the upper surface of the top electrode via.
1. An integrated chip comprising:
a memory cell overlying a substrate and comprising a top electrode;
a top electrode via overlying the top electrode, wherein a width of an upper surface of the top electrode via is greater than a width of a topmost surface of the top electrode, and wherein the width of the upper surface of the top electrode via is less than a width of a bottom surface of the top electrode and is greater than a height of the top electrode via;
a conductive via overlying and contacting the top electrode via, wherein a maximum width of the conductive via is greater than the width of the upper surface of the top electrode via, wherein the width of the upper surface of the top electrode via is less than a height of the conductive via; and
a conductive wire overlying and contacting the conductive via, wherein the conductive wire has a height less than the height of the conductive via and greater than the height of the top electrode via, wherein a width of a lower surface of the conductive wire is greater than the maximum width of the conductive via.
2. The integrated chip of claim 1 , wherein the memory cell further comprises a data storage structure under the top electrode, wherein the width of the upper surface of the top electrode via is less than a maximum width of the data storage structure.
3. The integrated chip of claim 1 , wherein a height of the upper surface of the top electrode via varies within a range of −25 angstroms to +25 angstroms from a horizontal line located between the upper surface of the top electrode via and a lower surface of the conductive via.
4. The integrated chip of claim 1 , wherein a distance between the upper surface of the top electrode via and the topmost surface of the top electrode is less than a height of the top electrode.
5. The integrated chip of claim 1 , wherein the memory cell further comprises a bottom electrode and a data storage structure disposed between the bottom electrode and the top electrode.
6. The integrated chip of claim 1 , wherein the conductive via comprises a protrusion that extends below the upper surface of the top electrode via.
7. The integrated chip of claim 1 , wherein a distance between opposing sidewalls of the top electrode continuously increases from the topmost surface of the top electrode in a first direction towards the substrate, wherein a distance between opposing sidewalls of the top electrode via continuously decreases from the upper surface of the top electrode via in the first direction.
8. The integrated chip of claim 1 , further comprising:
a first dielectric layer over the substrate, wherein the first dielectric layer is a single continuous layer, wherein the memory cell and the top electrode via are arranged in the first dielectric layer, wherein a bottom surface of the first dielectric layer is vertically below the bottom surface of the top electrode, wherein the first dielectric layer contacts sidewalls of the top electrode via, and wherein the upper surface of the top electrode via is aligned with an upper surface of the first dielectric layer.
9. An integrated chip comprising:
a first interlayer dielectric (ILD) layer overlying a substrate, wherein the first ILD layer is a single continuous layer comprising a first material;
a memory cell disposed within the first ILD layer, wherein the memory cell comprises a top electrode overlying a data storage structure, wherein the memory cell is disposed laterally within an embedded memory region;
a top electrode via within the first ILD layer and contacting the top electrode;
a conductive wire disposed laterally within a logic region that is laterally adjacent to the embedded memory region, wherein an upper surface of the conductive wire is vertically aligned with an upper surface of the top electrode via, wherein a lower surface of the conductive wire is vertically above a lower surface of the top electrode;
a lower conductive via disposed laterally within the logic region and directly below the conductive wire, wherein a height of the lower conductive via is greater than a height of the conductive wire; and
a second ILD layer disposed within the logic region and laterally enclosing the conductive wire, wherein an upper surface of the second ILD layer is vertically aligned with the upper surface of the top electrode via, and wherein a second material of the second ILD layer is different from the first material.
10. The integrated chip of claim 9 , wherein a width of the top electrode via continuously decreases from the upper surface of the top electrode via in a first direction towards the substrate, and wherein a width of the top electrode continuously increases from an upper surface of the top electrode in the first direction.
11. The integrated chip of claim 9 , wherein the data storage structure is configured as a magnetic tunnel junction (MTJ).
12. The integrated chip of claim 9 , wherein a slanted outer sidewall of the top electrode via directly overlies an outer edge of the top electrode.
13. The integrated chip of claim 9 , further comprising:
a conductive via overlying the top electrode via; and
an etch stop layer overlying the top electrode via and the conductive wire, wherein the etch stop layer continuously extends from the upper surface of the top electrode via to a sidewall of the conductive via.
14. The integrated chip of claim 13 , wherein the conductive via comprises a first conductive material and the top electrode via comprises a second conductive material different than the first conductive material.
15. The integrated chip of claim 9 , wherein a dielectric constant of the first ILD layer is less than a dielectric constant of the second ILD layer.
16. The integrated chip of claim 9 , wherein the second ILD layer is laterally offset from the top electrode via by a non-zero distance.
17. An integrated chip comprising:
a memory cell overlying a substrate and comprising a top electrode overlying a data storage structure;
a top electrode via arranged on the top electrode, wherein a width of an upper surface of the top electrode via is less than a width of the data storage structure, and wherein a height of the top electrode via is less than a height of the top electrode; and
a conductive interconnect arranged on the top electrode via and having a height greater than the height of the top electrode via, wherein the conductive interconnect comprises a protrusion that extends below the upper surface of the top electrode via and is disposed above a top surface of the top electrode, wherein the protrusion contacts a substantially straight slanted sidewall of the top electrode via that is adjacent to the upper surface of the top electrode via, wherein a first vertical distance between a bottommost surface of the protrusion and the top surface of the top electrode is greater than a second vertical distance between the bottommost surface of the protrusion and the upper surface of the top electrode via.
18. The integrated chip of claim 17 , wherein the memory cell comprises a bottom electrode under the data storage structure, wherein the substantially straight slanted sidewall of the top electrode via is spaced between opposing sidewalls of the bottom electrode.
19. The integrated chip of claim 17 , further comprising:
a first spacer structure arranged along sidewalls of the top electrode, wherein the top electrode via directly contacts the first spacer structure; and
a second spacer structure arranged on the first spacer structure and on opposing sides of the top electrode via, wherein the second spacer structure contacts the bottommost surface of the protrusion at a point below the upper surface of the top electrode via.
20. The integrated chip of claim 19 , wherein a top surface of the second spacer structure is disposed below the upper surface of the top electrode via, wherein the second spacer structure is vertically spaced from an upper surface of the top electrode by the first spacer structure.