IP Library › Granted Patent US 12,431,412
Granted Patent B2
US 12,431,412 · App. 18/356,031 · Granted Sep 30, 2025

Contact plugs for semiconductor device and method of forming same

Inventors: Mrunal A. Khaderbad (Hsinchu, TW); Yasutoshi Okuno (Hsinchu, TW); Sung-Li Wang (Zhubei, TW); Pang-Yen Tsai (Jhubei, TW); Shen-Nan Lee (Jhudong Township, TW); Teng-Chun Tsai (Hsinchu, TW)
Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
H01L23/485H01L21/02634H01L21/28562H01L21/31116H01L21/76814H01L21/76822H01L21/76826H01L21/76831H01L21/76846H01L21/76847H01L23/528H01L23/532H10D30/024H10D30/62H10D30/6219H10D62/151H10D62/83H10D64/017H10D64/20H10D64/23H10D64/62H10D84/0158H10D84/0193H10D84/038H10D30/797
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Quick Facts
Patent No.
US 12,431,412
App. No.
18/356,031
Granted
Sep 30, 2025
Kind
B2
Abstract

A semiconductor device and a method of forming the same are provided. A method includes forming a gate over a semiconductor structure. An epitaxial source/drain region is formed adjacent the gate. A dielectric layer is formed over the epitaxial source/drain region. An opening extending through the dielectric layer and exposing the epitaxial source/drain region is formed. A conductive material is non-conformally deposited in the opening. The conductive material fills the opening in a bottom-up manner.

Claims (44)

1. A device comprising:

a substrate comprising an active region;

a first epitaxial source/drain region extending into the active region;

a silicide layer over the first epitaxial source/drain region;

a first dielectric layer over the first epitaxial source/drain region;

a second dielectric layer over the first dielectric layer;

a first conductive feature in the second dielectric layer and extending through the first dielectric layer to the silicide layer;

a second conductive feature in the second dielectric layer and electrically coupled to the first conductive feature, wherein a bottom surface of the second conductive feature is a convex surface that is disposed in the second dielectric layer; and

a first barrier layer contacting a top surface of the first conductive feature and the bottom surface of the second conductive feature.

2. The device of claim 1 , wherein the top surface of the first conductive feature is a concave surface.

3. The device of claim 1 , wherein a bottom surface of the first barrier layer is a convex surface.

4. The device of claim 1 , wherein the first barrier layer further extends along sidewalls of the second conductive feature.

5. The device of claim 1 , wherein the first conductive feature has a same material composition throughout, and wherein the first conductive feature contacts sidewalls of the first dielectric layer.

6. The device of claim 1 , wherein the second conductive feature has a same material composition throughout, and wherein the second conductive feature contacts sidewalls of the second dielectric layer.

7. The device of claim 1 further comprising a contact etch stop layer (CESL) between the first epitaxial source/drain region and the first dielectric layer, wherein the first conductive feature extends through the CESL.

8. The device of claim 1 , wherein the first conductive feature and the second conductive feature have different material compositions.

9. A device comprising:

a first epitaxial source/drain region;

a first dielectric layer over the first epitaxial source/drain region;

a first contact in a first region of the first dielectric layer and electrically coupled to the first epitaxial source/drain region, wherein the first dielectric layer extends higher than the first contact;

a second dielectric layer between the first epitaxial source/drain region and the first dielectric layer, wherein the first contact extends through the second dielectric layer;

a second contact in a second region of the first dielectric layer and extending vertically from a top surface of the first dielectric layer to electrically couple to the first contact; and

a first barrier layer interposed between the first contact and second contact, wherein the first barrier layer extends from the top surface of the first dielectric layer to below a bottom surface of the second contact.

10. The device of claim 9 , wherein a bottom surface of the second contact and a bottom surface of the first barrier layer are each convex.

11. The device of claim 9 , wherein a bottom surface of the second contact and a bottom surface of the first barrier layer are each concave.

12. The device of claim 9 further comprising:

a gate stack in the second dielectric layer adjacent to the first epitaxial source/drain region.

13. The device of claim 9 , wherein a top surface of the first contact is wider than the bottom surface of the second contact.

14. The device of claim 9 , wherein the first barrier layer further extends along sidewalls of the second contact.

15. A device comprising:

a substrate;

a first epitaxial source/drain region extending into the substrate;

a silicide region in the first epitaxial source/drain region;

a first dielectric layer over the first epitaxial source/drain region;

a first contact disposed in the first dielectric layer and electrically coupled to the first epitaxial source/drain region, wherein the first contact has a same material composition throughout and has a sidewall that touches the first dielectric layer, and wherein the first contact overlaps and extends to the silicide region;

a second contact in the first dielectric layer and electrically coupled to the first contact, wherein the second contact overlaps the first contact;

a barrier layer between the first contact and second contact, wherein the barrier layer has a sidewall that touches the first dielectric layer, and wherein the barrier layer overlaps the first contact;

a second dielectric layer over the first dielectric layer; and

a third contact extending through the second dielectric layer, wherein the third contact overlaps and contacts top surfaces of the first dielectric layer, the second contact, and the barrier layer.

16. The device of claim 15 , wherein the second contact has a same material composition throughout and has a sidewall that touches the first dielectric layer.

17. The device of claim 15 , wherein the barrier layer extends along sidewalls of the second contact.

18. The device of claim 15 , wherein the second contact has a different material composition than the first contact.

19. The device of claim 15 , wherein a bottom surface of the barrier layer is curved.

20. The device of claim 15 , wherein the first contact extends continuously from the barrier layer to the silicide region.

Continuity (4)
Continuation 17101158 · Nov 23, 2020
Continuation 16112122 · Aug 24, 2018
Provisional Application 62592714 · Nov 30, 2017
Related Publication 20240021501A1 · Jan 18, 2024
References Cited (38)
US 6903011B2 · Liu · 2005 [cited by examiner]
US 8772109B2 · Colinge · 2014 [cited by applicant]
US 8785285B2 · Tsai et al. · 2014 [cited by applicant]
US 8816444B2 · Wann et al. · 2014 [cited by applicant]
US 8823065B2 · Wang et al. · 2014 [cited by applicant]
US 8860148B2 · Hu et al. · 2014 [cited by applicant]
US 9105490B2 · Wang et al. · 2015 [cited by applicant]
US 9236267B2 · De et al. · 2016 [cited by applicant]
US 9236300B2 · Liaw · 2016 [cited by applicant]
US 9502265B1 · Jiang et al. · 2016 [cited by applicant]
US 9520482B1 · Chang et al. · 2016 [cited by applicant]
US 9576814B2 · Wu et al. · 2017 [cited by applicant]
US 10008382B2 · Lin et al. · 2018 [cited by applicant]
US 10134872B2 · Chiou et al. · 2018 [cited by applicant]
US 20100099256A1 · Asako et al. · 2010 [cited by applicant]
US 20100155846A1 · Mukherjee et al. · 2010 [cited by applicant]
US 20120146223A1 · Zhao · 2012 [cited by examiner]
US 20140191400A1 · Chien et al. · 2014 [cited by applicant]
US 20150041854A1 · Wang · 2015 [cited by examiner]
US 20150179579A1 · Jezewski et al. · 2015 [cited by applicant]
US 20150206945A1 · Chen et al. · 2015 [cited by applicant]
US 20150243526A1 · Hsiao et al. · 2015 [cited by applicant]
US 20160190321A1 · Wang et al. · 2016 [cited by applicant]
US 20160336412A1 · Hung et al. · 2016 [cited by applicant]
US 20170186743A1 · Chiou et al. · 2017 [cited by applicant]
US 20200286836A1 · Jezewski et al. · 2020 [cited by applicant]
US 20200303184A1 · Lin et al. · 2020 [cited by applicant]
CN 101728320A · 2010 [cited by applicant]
CN 102239546A · 2011 [cited by applicant]
CN 106068549A · 2016 [cited by applicant]
CN 106409654A · 2017 [cited by applicant]
CN 106920751A · 2017 [cited by applicant]
JP 2012508989A · 2012 [cited by applicant]
KR 20170015062A · 2017 [cited by applicant]
KR 20170077771A · 2017 [cited by applicant]
KR 20170110000A · 2017 [cited by applicant]
WO 2010080276A2 · 2010 [cited by applicant]
Gall Daniel, “Electron Mean Free Path in Elemental Metals,” Journal of Applied Physics 119, 085101, Feb. 23, 2016, 6 pages. [cited by applicant]