IP Library Granted Patent US 12,433,165
Granted Patent B2
US 12,433,165 · App. 18/224,711 · Granted Sep 30, 2025

Method for manufacturing semiconductor module including piezoelectric layer

Inventor: Zhi-Biao Zhou (Singapore, SG)
Assignee: UNITED MICROELECTRONICS CORP.
H10N30/05H10N30/072
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Quick Facts
Patent No.
US 12,433,165
App. No.
18/224,711
Granted
Sep 30, 2025
Kind
B2
Abstract

A method for manufacturing a semiconductor module is provided. The method includes: providing a substrate, wherein the substrate comprises a front side and at least one semiconductor element formed on the front side; forming a shielding structure on the at least one semiconductor element; forming a piezoelectric layer on the shielding structure.

Claims (16)

1. A method for manufacturing a semiconductor module, comprising:

providing a substrate, wherein the substrate comprises a front side and at least one semiconductor element formed on the front side;

forming a shielding structure on the at least one semiconductor element;

forming a piezoelectric layer on the shielding structure;

forming a first protecting layer on the piezoelectric layer and a conductive structure passing through the piezoelectric layer and the first protecting layer; and

forming a second protecting layer covering an upper surface of the first protecting layer, an upper surface of the conductive structure and a sidewall of the piezoelectric layer, wherein a lower end of the second protecting layer is in the shielding structure, and the shielding structure comprises a magnetic material,

wherein the second protecting layer is directly on the sidewall of the piezoelectric layer, and the first protecting layer and the second protecting layer comprise dielectric materials.

2. The method according to claim 1 , further comprising:

forming a first buffer layer on the at least one semiconductor element prior to the forming the shielding structure on the at least one semiconductor element; and

forming a second buffer layer on the shielding structure prior to the forming the piezoelectric layer on the shielding structure.

3. The method according to claim 1 , wherein the shielding structure is deposited on the at least one semiconductor element.

4. The method according to claim 1 , wherein the piezoelectric layer is bonded to the shielding structure or deposited on the shielding structure.

5. The method according to claim 1 , wherein the forming the shielding structure on the at least one semiconductor element comprises:

forming a first shielding layer, wherein the first shielding layer has a first density and is stacked on the at least one semiconductor element; and

forming a second shielding layer, wherein the second shielding layer has a second density and is stacked on the first shielding layer.

6. The method according to claim 1 , wherein the forming the shielding structure on the at least one semiconductor element comprises forming the shielding structure having a gradient density.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 21, 2023
From: ZHOU, ZHI-BIAO
To: UNITED MICROELECTRONICS CORP.
Reel/Frame 064338/0658 →
Priority Claims (1)
CN 202010781779.0 · Aug 6, 2020 · national
Continuity (2)
Division 17022150 · Sep 16, 2020
Related Publication 20230363278A1 · Nov 9, 2023
References Cited (32)
US 4628490A · Kramer · 1986 [cited by applicant]
US 4758896A · Katsu · 1988 [cited by applicant]
US 5481915A · Tabota · 1996 [cited by applicant]
US 7968978B2 · Adlerstein · 2011 [cited by examiner]
US 9556321B2 · Curry · 2017 [cited by applicant]
US 9640639B2 · Yamazaki · 2017 [cited by examiner]
US 10062943B2 · Li · 2018 [cited by applicant]
US 10109474B1 · Wang et al. · 2018 [cited by applicant]
US 10141912B2 · Hurwitz · 2018 [cited by examiner]
US 10153342B1 · He et al. · 2018 [cited by applicant]
US 10262986B2 · Dai et al. · 2019 [cited by applicant]
US 10389331B2 · Hurwitz · 2019 [cited by applicant]
US 10460980B2 · Verma et al. · 2019 [cited by applicant]
US 12060264B2 · Li · 2024 [cited by examiner]
US 20020171508A1 · Harada et al. · 2002 [cited by applicant]
US 20030186521A1 · Kub · 2003 [cited by examiner]
US 20040173816A1 · Saxler · 2004 [cited by applicant]
US 20060214202A1 · Zorich · 2006 [cited by examiner]
US 20090091904A1 · Hatanaka · 2009 [cited by applicant]
US 20090218912A1 · Abd Allah · 2009 [cited by applicant]
US 20120133001A1 · Tkaczyk · 2012 [cited by applicant]
US 20140219063A1 · Hajati · 2014 [cited by applicant]
US 20150173237A1 · Lin · 2015 [cited by applicant]
US 20160011722A1 · Lin · 2016 [cited by applicant]
US 20170207214A1 · Or-Bach · 2017 [cited by applicant]
US 20180331156A1 · Then · 2018 [cited by applicant]
US 20190097599A1 · Taniguchi · 2019 [cited by applicant]
US 20190273116A1 · Goktepeli · 2019 [cited by applicant]
US 20200035625A1 · Wang · 2020 [cited by examiner]
US 20200152697A1 · Qian · 2020 [cited by applicant]
EP 1760770A2 · 2007 [cited by examiner]
EP 3474447A1 · 2019 [cited by applicant]