IP Library Granted Patent US 12,439,681
Granted Patent B2
US 12,439,681 · App. 18/613,151 · Granted Oct 7, 2025

Semiconductor device and method for fabricating the same

Inventors: Ching-Ling Lin (Kaohsiung, TW); Wen-An Liang (Tainan, TW); Chen-Ming Huang (Taipei, TW)
Assignee: UNITED MICROELECTRONICS CORP.
H10D84/038H01L21/764H10D30/024H10D30/62H10D62/115H10D64/017H10D84/0151H10D84/0158H10D84/834
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Quick Facts
Patent No.
US 12,439,681
App. No.
18/613,151
Granted
Oct 7, 2025
Kind
B2
Abstract

A semiconductor device includes a fin-shaped structure on a substrate, a gate structure on the fin-shaped structure and an interlayer dielectric (ILD) layer around the gate structure, and a single diffusion break (SDB) structure in the ILD layer and the fin-shaped structure. Preferably, the SDB structure includes a bottom portion and a top portion on the bottom portion, in which the top portion and the bottom portion include different widths.

Claims (21)

1. A semiconductor device, comprising:

a fin-shaped structure on a substrate;

a gate structure on the fin-shaped structure and an interlayer dielectric (ILD) layer around the gate structure;

an epitaxial layer adjacent to the gate structure;

a single diffusion break (SDB) structure in the ILD layer and the fin-shaped structure, wherein the SDB structure comprises:

a bottom portion comprising a first width and a second width, wherein a top surface of the bottom portion is higher than a top surface of the epitaxial layer; and

a top portion on the bottom portion, wherein the top portion comprise a third width and a top surface of the bottom portion is higher than a top surface of the fin-shaped structure.

2. The semiconductor device of claim 1 , further comprising:

a first spacer around the gate structure;

a second spacer around the SDB structure; and

a contact etch stop layer (CESL) between the first spacer and the second spacer.

3. The semiconductor device of claim 2 , wherein the first spacer and the second spacer comprise different heights.

4. The semiconductor device of claim 2 , wherein the CESL is U-shaped.

5. The semiconductor device of claim 2 , wherein a top surface of the CESL adjacent to the second spacer is lower than a top surface of the CESL adjacent to the first spacer.

6. The semiconductor device of claim 1 , wherein a top surface of the bottom portion is even with a top surface of the gate structure.

7. The semiconductor device of claim 1 , wherein the SDB structure comprises:

a liner; and

a dielectric layer on the liner, wherein the liner and the dielectric layer comprise different material.

8. The semiconductor device of claim 1 , further comprising an air gap in the SDB structure.

9. The semiconductor device of claim 1 , wherein the fin-shaped structure is disposed extending along a first direction and the SDB structure is disposed extending along a second direction.

10. The semiconductor device of claim 9 , wherein the first direction is orthogonal to the second direction.

Priority Claims (1)
CN 201711262580.1 · Dec 4, 2017 · national
Continuity (4)
Continuation 18088631 · Dec 26, 2022
Continuation 16859959 · Apr 27, 2020
Division 15859775 · Jan 2, 2018
Related Publication 20240282637A1 · Aug 22, 2024
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