IP Library Granted Patent US 12,476,213
Granted Patent B2
US 12,476,213 · App. 17/806,311 · Granted Nov 18, 2025

Semiconductor package and method of manufacturing

Inventors: Chien Li (Taoyuan, TW); Chih-Ju Yen (New Taipei, TW); Jui Hsien Lo (New Taipei, TW); Chien-Sheng Chen (Hsinchu, TW); Shin-Puu Jeng (Hsinchu, TW)
Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
H01L24/13H01L24/97H01L2224/11318H01L2224/116H01L2224/145H01L2224/97
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Quick Facts
Patent No.
US 12,476,213
App. No.
17/806,311
Granted
Nov 18, 2025
Kind
B2
Abstract

Some implementations described herein provide a semiconductor package including an integrated circuit die mounted to an interposer using connection structures. An underfill material between the integrated circuit die and the interposer includes shaped fillets that are below a plane corresponding to a bottom surface of the integrated circuit die. The underfill material including the shaped fillets reduces a likelihood of stresses and/or strains that damage a mold compound from transferring to the mold compound from the underfill material, the integrated circuit die, and/or the interposer. In this way, a quality and reliability of the semiconductor package including the underfill material with the shaped fillets is reduced. By improving the quality and reliability of the semiconductor package, a yield of the semiconductor package may increase to decrease a cost of the semiconductor package.

Claims (71)

1 . A semiconductor package, comprising:

an interposer;

an integrated circuit die mechanically and/or electrically connected to the interposer using a set of connection structures between the integrated circuit die and the interposer;

a mold compound over the integrated circuit die, the interposer, and the set of connection structures; and

an underfill pattern between the interposer and the integrated circuit die comprising:

a shaped fillet having a top surface at or below a plane corresponding to a bottom surface of the integrated circuit die,

wherein the shaped fillet comprises a curvature that intersects a portion of the bottom surface of the integrated circuit die at a distance from a bottom cornered edge of the integrated circuit die,

wherein a segment of the shaped fillet includes a portion that protrudes beyond a perimeter of the integrated circuit die, and

wherein the segment of the shaped fillet has a top surface at or below the plane corresponding to the bottom surface of the integrated circuit die.

2 . The semiconductor package of claim 1 , wherein the shaped fillet comprises:

a height that is lesser than or equal to a distance between the bottom surface of the integrated circuit die and a top surface of the interposer.

3 . The semiconductor package of claim 1 , wherein the shaped fillet comprises:

a concave surface extending towards the set of connection structures.

4 . A structure, comprising:

an interposer;

a first integrated circuit die and a second integrated circuit die adjacent to one another on the interposer and having edges that form an approximately rectangular perimeter; and

a pattern of an underfill material comprising segments of shaped fillets along the approximately rectangular perimeter,

wherein the segments of the shaped fillets include portions that protrude beyond the approximately rectangular perimeter,

wherein the segments of the shaped fillets include top surfaces that are at or below a first plane corresponding to a bottom surface of the first integrated circuit die and a second plane corresponding to a bottom surface of the second integrated circuit die, and

wherein the segments of the shaped fillets exclude top surfaces that are above the first plane corresponding to the bottom surface of the first integrated circuit die and the second plane corresponding to the bottom surface of the second integrated circuit die.

5 . The structure of claim 4 , wherein the portions that protrude beyond the approximately rectangular perimeter comprise:

midsegments along middle regions of first opposing sides of the approximately rectangular perimeter that are located adjacent to opposing ends of adjacent, mutually-facing regions of the first integrated circuit die and the second integrated circuit die, and

corner segments along corner regions of the approximately rectangular perimeter, and

wherein the portions that protrude beyond the approximately rectangular perimeter exclude:

other segments along the approximately rectangular perimeter between the corner segments and the midsegments, and

other segments along the approximately rectangular perimeter between the corner segments and along second opposing sides of the approximately rectangular perimeter.

6 . The structure of claim 4 , wherein the portions that protrude beyond the approximately rectangular perimeter comprise:

corner segments along corner regions of the approximately rectangular perimeter, and

wherein the segments of the shaped fillets exclude:

other segments along the approximately rectangular perimeter between the corner segments.

7 . The structure of claim 4 , wherein the portions that protrude beyond the approximately rectangular perimeter comprise:

linear segments along outer facing regions of the first integrated circuit die and the second integrated circuit die, and

midsegments along middle regions of first opposing sides of the approximately rectangular perimeter that are located adjacent to opposing ends of adjacent, mutually-facing regions of the first integrated circuit die and the second integrated circuit die,

wherein the segments of the shaped fillets exclude:

other segments along corner regions of the approximately rectangular perimeter.

8 . The structure of claim 4 , wherein the portions that protrude beyond the approximately rectangular perimeter comprise:

linear segments along outer facing regions of the first integrated circuit die and the second integrated circuit die, and

wherein the portions that protrude beyond the approximately rectangular perimeter exclude:

other segments along middle regions of first opposing sides of the approximately rectangular perimeter that are located adjacent to opposing ends of adjacent, mutually-facing regions of the first integrated circuit die and the second integrated circuit die, and

other segments along corner regions of the approximately rectangular perimeter.

9 . The structure of claim 4 , wherein the portions that protrude beyond the approximately rectangular perimeter comprise:

midsegments along middle regions of opposing sides of the approximately rectangular perimeter that are located adjacent to opposing ends of adjacent, mutually-facing regions of the first integrated circuit die and the second integrated circuit die, and

wherein the portions that protrude beyond the approximately rectangular perimeter exclude:

other segments along outer facing regions of the first integrated circuit die and the second integrated circuit die, and

other segments along corner regions of the approximately rectangular perimeter.

10 . The structure of claim 4 , wherein the segments of the shaped fillets further include:

portions that are retracted within the approximately rectangular perimeter.

11 . The structure of claim 4 , wherein the segments of the shaped fillets comprise:

segments having different shapes.

12 . A method, comprising:

attaching an integrated circuit die to an interposer using a set of connection structures;

forming an underfill pattern, between the integrated circuit die and the interposer, comprising a concave-shaped fillet,

wherein the concave-shaped fillet is completely below a plane corresponding to a bottom surface of the integrated circuit die,

wherein the concave-shaped fillet comprises a curvature that intersects a portion of the bottom surface of the integrated circuit die at a distance from a bottom cornered edge of the integrated circuit die, and

wherein forming the underfill pattern includes:

performing a first dispense operation that forms a first portion of the underfill pattern around the set of connection structures, and

performing a second dispense operation that forms a second portion of the underfill pattern adjacent to the set of connection structures,

wherein the second portion of the underfill pattern includes the concave-shaped fillet; and

forming a mold compound over the integrated circuit die, the interposer, and the underfill pattern.

13 . The method of claim 12 , wherein performing the first dispense operation includes dispensing a first type of material, and

wherein performing the second dispense operation includes dispensing the first type of material.

14 . The method of claim 12 , wherein performing the first dispense operation includes dispensing a first type of material, and

wherein performing the second dispense operation includes dispensing a second type of material that is other than the first type of material.

15 . The method of claim 12 , wherein performing the second dispense operation includes dispensing a material that, in cured form, possesses a coefficient of thermal expansion that is included in a range of approximately 10 microns per meter Kelvin (μ/m K) to approximately 50 μ/m K, and

wherein the material further possesses a Young's modulus that is included in a range of approximately 1 gigapascal (GPa) to approximately 20 gigapascals GPa.

16 . The method of claim 12 , further comprising:

bonding the interposer to a temporary carrier prior to attaching the integrated circuit die to the interposer and prior to forming the underfill pattern.

17 . The semiconductor package of claim 1 , wherein the distance is up to approximately 200 μm.

18 . The semiconductor package of claim 1 , wherein an apex of the shaped fillet is located up to 200 μm from the bottom cornered edge of the integrated circuit die.

19 . The method of claim 12 , wherein the distance is up to approximately 200 μm.

20 . The structure of claim 4 , wherein the segments of the shaped fillets include segments having one or more of a concave shape or a triangular shape.

Assignments (2)
CORRECTIVE ASSIGNMENT TO CORRECT THE THE FIRST NAME OF THE FIRST INVENTOR PREVIOUSLY RECORDED AT REEL: 060185 FRAME: 0287. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT. Recorded Jul 20, 2022
From: LI, CHIEN; YEN, CHIH-JU; LO, JUI HSIEN; CHEN, CHIEN-SHENG; JENG, SHIN-PUU
To: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
Reel/Frame 060777/0164 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 13, 2022
From: LI, LEO; YEN, CHIH-JU; LO, JUI HSIEN; CHEN, CHIEN-SHENG; JENG, SHIN-PUU
To: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
Reel/Frame 060185/0287 →
Continuity (1)
Related Publication 20230402417A1 · Dec 14, 2023
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