IP Library Granted Patent US 12,482,665
Granted Patent B2
US 12,482,665 · App. 18/105,336 · Granted Nov 25, 2025

Method of manufacturing semiconductor structure

Inventor: Hsuan-Wu Lai (Yilan, TW)
Assignee: NANYA TECHNOLOGY CORPORATION
H01L21/31122H01L21/0243H01L21/02488H01L21/02532H01L21/0262H01L21/02658H01L21/02115H01L21/02271H01L21/02592H01L21/02595
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Quick Facts
Patent No.
US 12,482,665
App. No.
18/105,336
Granted
Nov 25, 2025
Kind
B2
Abstract

A method of manufacturing a semiconductor structure is provided. The method includes providing a semiconductor wafer having a central region and a bevel region; forming a first material layer over the central region and the bevel region of the semiconductor wafer; performing a dry etching operation on a portion of the first material layer over the bevel region of the semiconductor wafer; performing a wet etching operation on the portion of the first material layer over the bevel region of the semiconductor wafer; performing a baking operation on the bevel region of the semiconductor wafer; and forming a second material layer on the central region and the bevel region of the semiconductor wafer after performing the baking operation.

Claims (17)

1 . A method of manufacturing a semiconductor structure, comprising:

providing a semiconductor wafer having a central region and a bevel region;

forming a first material layer over the central region and the bevel region of the semiconductor wafer;

performing a dry etching operation on a portion of the first material layer over the bevel region of the semiconductor wafer;

performing a wet etching operation on the portion of the first material layer over the bevel region of the semiconductor wafer;

performing a baking operation on the bevel region of the semiconductor wafer; and

forming a second material layer on the central region and the bevel region of the semiconductor wafer after performing the baking operation.

2 . The method of claim 1 , wherein the first material layer and the second material layer are formed of different materials.

3 . The method of claim 1 , wherein the first material layer comprises diamond-like carbon, and the second material layer comprises amorphous silicon.

4 . The method of claim 3 , wherein the dry etching operation comprises a plasma dry etching operation using oxygen gas as an etching gas.

5 . The method of claim 1 , wherein forming the second material layer and performing the baking operation are performed in an in-situ manner.

6 . The method of claim 1 , wherein the wet etching operation is performed by using a mixture comprising ammonia (NH 4 OH) and hydrogen peroxide (H 2 O 2 ) as an etching solution.

7 . The method of claim 1 , wherein a temperature for forming the second material layer and a temperature for performing the baking operation are substantially the same.

8 . The method of claim 1 , wherein the baking operation is performed under a temperature from about 350° C. to about 450° C. and for about 90 seconds to about 150 seconds.

9 . The method of claim 1 , further comprising:

forming a third material layer on the second material layer over the central region and the bevel region of the semiconductor wafer, wherein the third material layer is different from the second material layer.

10 . The method of claim 9 , wherein the first material layer and the second material layer are formed by chemical vapor deposition, and the third material layer is formed by spin-coating.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Mar 8, 2023
From: LAI, HSUAN-WU
To: NANYA TECHNOLOGY CORPORATION
Reel/Frame 062917/0419 →
Continuity (1)
Related Publication 20240266184A1 · Aug 8, 2024
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