Ground via clustering for crosstalk mitigation
Embodiments of the present disclosure are directed towards techniques and configurations for ground via clustering for crosstalk mitigation in integrated circuit (IC) assemblies. In some embodiments, an IC package assembly may include a first package substrate configured to route input/output (I/O) signals and ground between a die and a second package substrate. The first package substrate may include a plurality of contacts disposed on one side of the first package substrate and at least two ground vias of a same layer of vias, and the at least two ground vias may form a cluster of ground vias electrically coupled with an individual contact. Other embodiments may be described and/or claimed.
1 . A semiconductor package, comprising:
a substrate having a die side and a second side opposite the die side; and
a plurality of ball pads on the second side of the substrate, individual ones of the plurality of ball pads having a first side opposite a second side, and individual ones of the plurality of ball pads having a first vertical interconnect structure, a second vertical interconnect structure, and a third vertical interconnect structure coupled directly to the first side of the ball pad, each of the first vertical interconnect structure, the second vertical interconnect structure, and the third vertical interconnect structure comprising a corresponding stack of vias.
2 . The semiconductor package of claim 1 , further comprising:
a plurality of solder balls, individual ones of the plurality of solder balls coupled to the second side of a corresponding one of the plurality of ball pads.
3 . The semiconductor package of claim 2 , wherein the first vertical interconnect structure, the second vertical interconnect structure, and the third vertical interconnect structure are coupled directly to the first side of the corresponding one of the plurality of ball pads and are within a footprint of the corresponding individual one of the plurality of solder balls.
4 . The semiconductor package of claim 1 , further comprising:
a die coupled to the die side of the substrate.
5 . The semiconductor package of claim 1 , further comprising:
an interposer coupled to the second side of the substrate.
6 . The semiconductor package of claim 5 , wherein the interposer is coupled to the second side of the substrate by a plurality of solder balls, individual ones of the plurality of solder balls coupled to the second side of a corresponding one of the plurality of ball pads.
7 . The semiconductor package of claim 6 , wherein the first vertical interconnect structure, the second vertical interconnect structure, and the third vertical interconnect structure are coupled directly to the first side of the corresponding one of the plurality of ball pads and are within a footprint of the corresponding individual one of the plurality of solder balls.
8 . The semiconductor package of claim 1 , wherein each corresponding stack of vias has at least three vias.
9 . The semiconductor package of claim 1 , wherein one of the plurality of ball pads is coupled to ground.
10 . The semiconductor package of claim 1 , wherein the first vertical interconnect structure, the second vertical interconnect structure, and the third vertical interconnect structure extend from the die side of the substrate to the second side of the substrate.
11 . A semiconductor package, comprising:
a substrate having a die side and a second side opposite the die side; and
a plurality of ball pads on the second side of the substrate, individual ones of the plurality of ball pads having a first side opposite a second side, and individual ones of the plurality of ball pads having a first vertical interconnect structure and a second vertical interconnect structure coupled directly to the first side of the ball pad, each of the first vertical interconnect structure and the second vertical interconnect structure comprising a corresponding stack of vias.
12 . The semiconductor package of claim 11 , further comprising:
a plurality of solder balls, individual ones of the plurality of solder balls coupled to the second side of a corresponding one of the plurality of ball pads.
13 . The semiconductor package of claim 12 , wherein the first vertical interconnect structure and the second vertical interconnect structure are coupled directly to the first side of the corresponding one of the plurality of ball pads and are within a footprint of the corresponding individual one of the plurality of solder balls.
14 . The semiconductor package of claim 11 , further comprising:
a die coupled to the die side of the substrate.
15 . The semiconductor package of claim 11 , further comprising:
an interposer coupled to the second side of the substrate.
16 . The semiconductor package of claim 15 , wherein the interposer is coupled to the second side of the substrate by a plurality of solder balls, individual ones of the plurality of solder balls coupled to the second side of a corresponding one of the plurality of ball pads.
17 . The semiconductor package of claim 16 , wherein the first vertical interconnect structure and the second vertical interconnect structure are coupled directly to the first side of the corresponding one of the plurality of ball pads and are within a footprint of the corresponding individual one of the plurality of solder balls.
18 . The semiconductor package of claim 11 , wherein each corresponding stack of vias has at least three vias.
19 . The semiconductor package of claim 11 , wherein one of the plurality of ball pads is coupled to ground.
20 . The semiconductor package of claim 11 , wherein the first vertical interconnect structure and the second vertical interconnect structure extend from the die side of the substrate to the second side of the substrate.