Granted Patent B2

US 12,493,492 · App. 18/423,184 · Granted Dec 9, 2025

Inventor: Mark Henrik Sandstrom (Alexandria, VA)

Assignee: ThroughPuter, Inc.

G06F9/5011G06F9/46G06F9/4881G06F9/5016G06F9/5027G06F9/5038G06F9/505G06F9/54G06F9/544G06F9/546G06F15/17337H04L49/15

Abstract

Claims (22)

1 . A method for parallel processing of multiple packet streams comprising:

receiving, at at least one input port, multiplexed data packets corresponding to a plurality of concurrent data packet streams, at least two of the plurality of concurrent data packet streams associated with different program instances of at least one program hosted by the system,

providing a plurality of stream-specific input packet buffers, each buffer specific to a corresponding packet stream of the plurality of data packet streams, during a respective time interval for that stream;

providing at least one output port to transmit output data streams corresponding to the input data streams;

demultiplexing, at hardware-implemented demultiplexer logic, the multiplexed data packets received at the at least one input port into the corresponding stream-specific packet buffers;

providing a plurality of processing cores implemented in a reconfigurable hardware fabric, each core configured to execute at least one program instance task on the data packets associated with at least one of the plurality of data packet streams;

reconfiguring, at a hardware-implemented controller, one or more of the processing cores or the reconfigurable fabric to perform different program instance tasks on one or more of the data packet streams or to perform program instance tasks on one or more of the data packet streams in a different order,

identifying, at the hardware-implemented controller, a processing core to which each of a plurality of the data packets in one or more of the stream-specific input packet buffers is to be transmitted;

directing, at hardware-implemented multiplexing logic, for each respective input packet buffer of the stream-specific input packet buffers, data packets from the respective input packet buffer to the appropriate one of the processing cores; and

transmitting, at a hardware-implemented interconnect, at least some of the data packets to a plurality of different ones of the processing cores and to transmit packets associated with each output data stream to the output port.

2 . The method of claim 1 , wherein the processing cores form a multi-stage parallel data processing platform.

3 . The method of claim 1 , wherein the hardware-implemented controller and the hardware-implemented interconnect cooperate to connect data packets to processing cores based at least in part based on volumes of data packets connected through the interconnect, wherein a volume of input data packets refers to one of volume of data across the packets, or number of the packets.

4 . The method of claim 1 , further comprising providing isolation between the data packet streams based on an identification contained in each data packet that associates the packet with a respective packet stream.

5 . The method of claim 1 , wherein the program instance tasks are instantiated across at least a certain subset of the processing cores to provide an equalized expected aggregate task processing load across the subset of processing cores.

6 . The method of claim 1 , further comprising configuring at least the processing cores to support execution of a multi-stage program task comprising:

instantiating a first program instance task of the multi-stage program on at least one of the processing cores, the at least one of the processing cores performing the first program instance task comprising a first processing unit;

instantiating a second program instance task of the multi-stage program on at least one other of the processing cores, the at least one other of the processing cores performing the second program instance task comprising a second processing unit;

configuring the first processing unit and/or the interconnect to transmit output data packets to the second processing unit.

7 . The method of claim 6 , wherein the output data packets are transmitted to a processing core of the second processing unit based on a load measured at one or more input buffers associated with one or more of the processing cores.

8 . The method of claim 1 , wherein the hardware-implemented controller and hardware implemented interconnect operate without software involvement.

9 . The method of claim 1 , wherein the hardware-implemented controller periodically assigns instances of the tasks for execution on the plurality of processing cores.

10 . The method of claim 9 , wherein the assigning provides an equalized expected aggregate task processing load across at least a subset of the processing cores.

Continuity (24)

References Cited (400)