Granted Patent B2

US 12,532,737 · App. 17/742,666 · Granted Jan 20, 2026

Inventors: Kushal Kshirsagar (Warwick, RI); Eung San Cho (Torrance, CA); Arun Kumar Gnanappa (Regensburg, DE); Wenkang Huang (East Greenwich, RI); Angela Kessler (Sinzing, DE); Marcel Rene Mueller (Bendorf, DE); Stephen Pullen (Olympia, WA)

Assignee: Infineon Technologies AG

H01L23/3675H01L21/4853H01L21/4871H01L23/49838H01L24/16H01L2224/16227H01L2924/19042H01L2924/19105

Abstract

Claims (16)

1 . A semiconductor assembly, comprising:

a device carrier that comprises a dielectric core region and a plurality of contact pads disposed on an upper surface of the device carrier;

a semiconductor device package comprising a plurality of lower surface terminals,

a discrete passive element comprising a main body and a pair of leads exposed from the main body; and

a region of gap filler material,

wherein the semiconductor device package is mounted on the device carrier with the lower surface terminals facing and electrically connected to a group of the contact pads,

wherein the discrete passive element is mounted on the device carrier with the pair of leads electrically connecting with contact surfaces on the device carrier, and

wherein the region of gap filler material is arranged between a lower surface of the main body and the upper surface of the semiconductor device package and thermally couples the semiconductor device package to the discrete passive element.

2 . The semiconductor assembly of claim 1 , wherein the semiconductor device package is an embedded package that comprises a power semiconductor die embedded within a laminate package body.

3 . The semiconductor assembly of claim 2 , wherein the discrete passive element is a discrete inductor.

4 . The semiconductor assembly of claim 1 , wherein the pair of leads is electrically connected to a pair of the contact pads that are arranged on opposite sides of the semiconductor device package.

5 . The semiconductor assembly of claim 1 , wherein the device carrier comprises a pair of contact trenches that are arranged on opposite sides of the semiconductor device package, wherein the pair of contact trenches each comprise a solderable plating that lines a bottom surface and sidewall surfaces of the contact trenches, and wherein the pair of leads is electrically connected to the solderable plating from the pair of contact trenches.

6 . The semiconductor assembly of claim 5 , further comprising a flowable electrical connection material disposed within the pair of contact trenches, and wherein the pair of leads is arranged within the contact trenches such that ends of both of the leads are separated from the bottom surfaces of the contact trenches by the flowable electrical connection material.

7 . The semiconductor assembly of claim 1 , further comprising a second device carrier that comprises a dielectric core region and a plurality of contact pads disposed on an upper surface of the second device carrier, wherein the device carrier is mounted on the second device carrier, and wherein the device carrier is an interposer comprising contact pads disposed on a lower surface of the device carrier, and wherein the device carrier electrically connects one or more of the lower surface terminals of the semiconductor device package to the contact pads disposed on the upper surface of the second device carrier.

8 . The semiconductor assembly of claim 1 , wherein the device carrier is a printed circuit board with a plurality of electrical devices mounted thereon.

9 . The semiconductor assembly of claim 1 , wherein the gap filler material is a thermal interface material.

Assignments (3)

Continuity (1)

References Cited (25)