Granted Patent B2

US 12,567,351 · App. 18/718,315 · Granted Mar 3, 2026

Inventors: Susumu Kawashima (Atsugi, JP); Koji Kusunoki (Isehara, JP); Tomoaki Atsumi (Hadano, JP); Naoto Kusumoto (Isehara, JP)

Assignee: Semiconductor Energy Laboratory Co., Ltd.

G09G3/2081G09G3/2011G09G3/2014G09G3/32H01L25/167H10D86/423H10D86/60G09G2300/0852G09G2310/08

Abstract

Claims (26)

1 . A display device comprising a pulse signal generation portion, a first node, a second node, a first transistor, a second transistor, a third transistor, a first capacitor, and a light-emitting device in a pixel,

wherein the first node is electrically connected to one of a source and a drain of the first transistor, one of a source and a drain of the second transistor, and an input portion of the pulse signal generation portion,

wherein the second node is electrically connected to the other of the source and the drain of the second transistor, a gate of the third transistor, one electrode of the first capacitor, and an output portion of the pulse signal generation portion,

wherein one of a source and a drain of the third transistor is electrically connected to one electrode of the light-emitting device,

wherein the other of the source and the drain of the third transistor is electrically connected to the other electrode of the first capacitor,

wherein the pulse signal generation portion comprises fourth to ninth transistors and a second capacitor,

wherein the fourth transistor comprises a first gate and a second gate,

wherein the first gate of the fourth transistor and one of a source and a drain of the fifth transistor are electrically connected to the first node,

wherein one of a source and a drain of the fourth transistor is electrically connected to a gate of the sixth transistor and one of a source and a drain of the seventh transistor,

wherein the second gate of the fourth transistor is electrically connected to one of a source and a drain of the eighth transistor and one electrode of the second capacitor,

wherein the other electrode of the second capacitor is electrically connected to one of a source and a drain of the ninth transistor,

wherein the other of the source and the drain of the ninth transistor is electrically connected to the other of the source and the drain of the fourth transistor, and

wherein one of a source and a drain of the sixth transistor is electrically connected to the second node.

2 . The display device according to claim 1 ,

wherein a signal potential with a ramp waveform is input to the other of the source and the drain of the fourth transistor.

3 . The display device according to claim 1 ,

wherein the first transistor, the second transistor, the fourth transistor, the fifth transistor, the eighth transistor, and the ninth transistor are each an n-channel transistor, and the third transistor, the sixth transistor, and the seventh transistor are each a p-channel transistor.

4 . The display device according to claim 3 ,

wherein the n-channel transistor comprises a metal oxide in a channel formation region, and the p-channel transistor comprises silicon in a channel formation region.

5 . The display device according to claim 1 ,

wherein the pixel makes the light-emitting device emit light in accordance with a data potential input to the first node,

wherein the pulse signal generation portion generates a pulse signal in accordance with the data potential input to the second node, and

wherein the pixel resets a potential of the first node in accordance with the pulse signal and makes the light-emitting device turn off.

6 . The display device according to claim 1 ,

wherein the light-emitting device is a micro LED.

7 . An electronic device comprising the display device according to claim 1 and a camera.

Assignments (1)

Priority Claims (1)

Continuity (1)

References Cited (62)