Semiconductor controlled rectifier and method to form same
Embodiments of the disclosure provide a semiconductor controlled rectifier (SCR) structure and methods to form the same. The SCR structure may include a first polycrystalline semiconductor material on a first insulator and includes a first well therein. A monocrystalline semiconductor material is adjacent the first polycrystalline semiconductor material and includes an anode region and a cathode region therein. A second polycrystalline semiconductor material is on a second insulator and includes a second well therein.
1 . A structure comprising:
a first polycrystalline semiconductor material on a first insulator, and including a first well therein, wherein a lower surface of the first polycrystalline semiconductor material interfaces with an upper surface of the first insulator;
a monocrystalline semiconductor material adjacent the first polycrystalline semiconductor material, and including an anode region and a cathode region therein, wherein the anode region and the cathode region each have a different depth below an upper surface of the monocrystalline semiconductor material; and
a second polycrystalline semiconductor material on a second insulator, laterally distal to the monocrystalline semiconductor material and including a second well therein, wherein a lower surface of the second polycrystalline semiconductor material interfaces with an upper surface of the second insulator, and the anode region and the cathode region each include a lower portion adjacent a respective one of the first insulator or the second insulator.
2 . The structure of claim 1 , wherein the monocrystalline semiconductor material includes a first region having a first doping type and a second region having a second doping type opposite the first doping type, wherein the anode region is within the first region and the cathode region is in the second region.
3 . The structure of claim 2 , further comprising a gate structure on the monocrystalline semiconductor material between the anode region and the cathode region, and over a boundary between the first region and the second region of the monocrystalline semiconductor material.
4 . The structure of claim 3 , further comprising:
a first overlying insulator on the first polycrystalline semiconductor material between the first well and the anode region; and
a second overlying insulator on the second polycrystalline semiconductor material between the second well and the cathode region.
5 . The structure of claim 1 , further comprising a resistive semiconductor material below the first insulator, the monocrystalline semiconductor material, and the second insulator.
6 . The structure of claim 1 , wherein the monocrystalline semiconductor material includes a first sidewall adjacent the first polycrystalline semiconductor material and the first insulator, and a second sidewall adjacent the second polycrystalline semiconductor material and the second insulator.
7 . The structure of claim 1 , wherein the monocrystalline semiconductor material is within a triple well semiconductor structure.
8 . A method comprising:
forming a first polycrystalline semiconductor material on a first insulator, wherein a lower surface of the first polycrystalline semiconductor material interfaces with an upper surface of the first insulator;
forming a first well within the first polycrystalline semiconductor material;
forming a monocrystalline semiconductor material adjacent the first polycrystalline semiconductor material;
forming an anode region and a cathode region within the monocrystalline semiconductor material;
forming a second polycrystalline semiconductor material on a second insulator and laterally distal to the monocrystalline semiconductor material, wherein a lower surface of the second polycrystalline semiconductor material interfaces with an upper surface of the second insulator, and the anode region and the cathode region each have a different depth below an upper surface of the monocrystalline semiconductor material; and
forming a second well within the second polycrystalline semiconductor material, wherein the anode region and the cathode region each include a lower portion adjacent a respective one of the first insulator or the second insulator.
9 . The method of claim 8 , wherein forming the monocrystalline semiconductor material includes:
forming a first region having a first doping type adjacent the first polycrystalline semiconductor material; and
forming a second region having a second doping type opposite the first doping type adjacent the second polycrystalline semiconductor material, wherein the anode region is within the first region and the cathode region is in the second region.
10 . The method of claim 9 , further comprising forming a gate structure on the monocrystalline semiconductor material between the anode region and the cathode region, and over a boundary between the first region and the second region of the monocrystalline semiconductor material.
11 . The method of claim 10 , further comprising:
forming a first overlying insulator on the first polycrystalline semiconductor material between the first well and the anode region; and
forming a second overlying insulator on the second polycrystalline semiconductor material between the second well and the cathode region.
12 . The method of claim 8 , wherein forming the monocrystalline semiconductor material includes forming the monocrystalline semiconductor material over a resistive semiconductor material, wherein the resistive semiconductor material is below the first insulator and the second insulator.
13 . The method of claim 8 , wherein the monocrystalline semiconductor material includes a first sidewall adjacent the first polycrystalline semiconductor material and the first insulator, and a second sidewall adjacent the second polycrystalline semiconductor material and the second insulator.
14 . The method of claim 8 , wherein forming the monocrystalline semiconductor material includes forming a doped semiconductor within a triple well semiconductor structure.