Power routing for 2.5D or 3D integrated circuits including a buried power rail and interposer with power delivery network
Embodiments relate to an electronic circuit implemented using a first integrated circuit die, a second integrated circuit die, and an interposer connecting the first integrated circuit die to the second integrated circuit die. The first integrated circuit die implements a first electronic circuit. The first integrated circuit die includes a first set of contacts on a bottom surface, a buried power rail (BPR), and a plurality of through-silicon vias (TSV) for connecting the BPR to the first set of contacts. The interposer includes a second set of contacts and a power delivery network (PDN). Each contact of the second set of contact corresponds to a contact of the first set of contacts of the first integrated circuit die. The PDN is configured to route a power supply voltage to the second set of contacts.
1 . An interposer comprising:
a first substrate;
a first set of contacts supported by the first substrate, the first set of contacts corresponding to a second set of contacts of an integrated circuit die, the integrated circuit die comprising a second substrate containing an active layer with active components; and
a power delivery network (PDN) supported by the first substrate, the PDN coupled to the first set of contacts, the PDN for routing a power supply voltage to each of the first set of contacts for providing power to the active components.
2 . The interposer of claim 1 , wherein:
the integrated circuit comprises: a buried power rail (BPR) disposed within the second substrate of the integrated circuit die, and a plurality of through-silicon vias (TSV), each TSV of the plurality of TSVs having a first end coupled to the BPR; and
the PDN in the interposer routes the power supply voltage to the plurality of TSVs via the first set of contacts, and the plurality of TSVs provide the supply voltage to multiple locations within the BPR.
3 . The interposer of claim 2 , wherein each of the first set of contacts routes the power supply voltage to one or more of the TSVs.
4 . The interposer of claim 1 , wherein a top surface of the interposer is configured to be bonded to a bottom surface of the integrated circuit die.
5 . The interposer of claim 1 , wherein the integrated circuit die is fabricated using a first fabrication process node and wherein the interposer is fabricated using a second fabrication process node, and the second fabrication process node uses a larger size geometry than the first fabrication process node.
6 . The interposer of claim 1 , further comprising:
a third set of contacts configured to be connected to an external system, wherein the PDN is further configured to couple one or more contacts of the third set of contacts to the second set of contacts.
7 . The interposer of claim 6 , wherein the first set of contacts are disposed on a first surface of the interposer, and wherein the third set of contacts are disposed on a second surface of the interposer opposite to the first surface.
8 . The interposer of claim 7 , wherein a pitch of the third set of contacts is larger than a pitch of the first set of contacts.
9 . The interposer of claim 1 , wherein the PDN comprises a plurality of interconnects for connecting the first set of contacts to each other.
10 . The interposer of claim 1 , wherein the first set of contacts are periodically arranged on a top surface of the interposer.
11 . The interposer of claim 1 , further comprising:
a third set of contacts supported by the first substrate, the third set of contacts corresponding to a fourth set of contacts of a second integrated circuit die, the second integrated circuit die comprising a third substrate containing an active layer with active components; and
I/O interconnects supported by the first substrate, the I/O interconnects coupling the first set of contacts with the third set of contacts.
12 . The interposer of claim 11 , wherein the integrated circuit die comprises a logic circuit, and the second integrated circuit die comprises a high bandwidth memory.
13 . The interposer of claim 11 , further comprising:
a fifth set of contacts configured to be connected to an external system, wherein the PDN is further configured to couple one or more contacts of the fifth set of contacts to the first and third sets of contacts.
14 . The interposer of claim 13 , wherein a pitch of the fifth set of contacts is larger than a pitch of the first set of contacts and larger than a pitch of the third set of contacts.
15 . The interposer of claim 1 , wherein the first set of contacts comprises micro solder balls or micro solder.
16 . The interposer of claim 1 , wherein the first set of contacts comprises pads.
17 . The interposer of claim 1 , wherein the first substrate is a silicon substrate.
18 . The interposer of claim 1 , wherein the PDN contains interconnects without any passive or active components.
19 . The interposer of claim 1 , wherein the integrated circuit die does not include a back side power delivery network.
20 . The interposer of claim 1 , wherein the PDN routes multiple power supply voltages to the first set of contacts.