Continuous NAND data-transfer with dynamic TM
The present disclosure generally relates to data storage devices, such as solid state drives (SSDs), and, more specifically, continuous data-transfer to and from a memory device of the data storage device. A data storage device includes a memory device and a controller coupled to the memory device. The controller is configured to indirectly delay the transfer without stopping toggling the DQS signals. The toggle mode (TM) speed is dynamically modified slowly during the transfer while considering the current level of the internal write buffer just before writing to the memory device. The transfer can now be accelerated or deaccelerated dynamically during the data transfer. The changes are done slowly so signal integrity issues are avoided.
1 . A data storage device, comprising:
a memory device; and
a controller coupled to the memory device, wherein the controller is configured to:
determine a level of fullness of a write buffer, wherein the determining comprises determining whether the write buffer has exceeded a buffer fullness level threshold of encoded write command data;
determine a filling/emptying rate of the write buffer;
adjust a toggle mode (TM) speed based upon the determining, wherein adjusting a TM speed comprises changing a pulse width of a data strobe (DQS) signal based on a speed of the filling/emptying rate of the write buffer, wherein the adjusting occurs during data transfer;
when a fill rate of the write buffer is determined to be insufficient to maintain a continuous data transfer, schedule garbage data writes to the memory device; and
write garbage data to the memory device when the write buffer is empty.
2 . The data storage device of claim 1 , wherein the adjusting comprises adjusting the TM speed by an amount of between about 1 percent and about 10 percent.
3 . The data storage device of claim 1 , wherein the adjusting is performed dynamically.
4 . The data storage device of claim 1 , wherein the adjusting comprises gradually changing the TM speed.
5 . The data storage device of claim 1 , wherein the adjusting is performed within a flash interface module (FIM) by a toggle mode adapter coupled to the write buffer.
6 . The data storage device of claim 5 , wherein the FIM also comprises a scheduler.
7 . The data storage device of claim 1 , wherein the write buffer has fullness thresholds.
8 . A data storage device, comprising:
a memory device; and
a controller coupled to the memory device, wherein the controller includes:
a write buffer;
a read buffer; and
a flash interface module (FIM), wherein:
the FIM is coupled to the memory device,
the FIM is coupled to the write buffer,
the FIM is coupled to the read buffer,
the FIM includes a toggle mode (TM) adapter and a scheduler, and
the TM adapter is configured to adjust a data strobe signal (DQS) dynamically based upon fullness of either: the write buffer, the read buffer, or both, and upon a speed of a filling/emptying rate of the write buffer, the read buffer, or both,
adjusting the DQS dynamically comprises increasing or decreasing a pulse width of the DQS,
the adjusting is based upon determining whether the write buffer has exceeded a buffer fullness level threshold of encoded write command data,
the TM adapter is configured to dynamically adjust the DQS during data transfer,
when a fill rate of the write buffer is determined to be insufficient to maintain a continuous data transfer, the controller is configured to schedule garbage data writes to the memory device,
when an empty rate of the read buffer is determined to be insufficient to maintain a continuous data transfer, the controller is configured to pause sampling data, and
the controller is configured to write garbage data to the memory device when the write buffer is empty.
9 . The data storage device of claim 8 , wherein the adapter is configured to ensure write buffer does not empty by adjusting TM speed.
10 . The data storage device of claim 8 , wherein the adjusting comprises changing the pulse width by a predetermined amount.
11 . The data storage device of claim 10 , wherein two consecutive pulses having different pulse widths.
12 . The data storage device of claim 8 , wherein the controller is configured to transfer data in a read path without sampling the data.
13 . A data storage device, comprising:
memory means; and
a controller coupled to the memory means, wherein the controller is configured to:
determine a filling/emptying rate of a write buffer;
dynamically adjust a data strobe signal (DQS) toggle mode (TM) pulse width in response to determining that the write buffer fullness threshold of encoded write command data has been crossed and based on a speed of the filling/emptying rate of the write buffer, wherein the write buffer is distinct from the memory means, wherein the adjusting occurs during data transfer;
when a fill rate of the write buffer is determined to be insufficient to maintain a continuous data transfer, schedule garbage data writes to the memory means; and
write garbage data to the memory means when the write buffer is empty.
14 . The data storage device of claim 13 , wherein the dynamically adjusting comprises decreasing TM pulse width.
15 . The data storage device of claim 13 , wherein when the write buffer is empty, the controller writes garbage data to the memory means.