Metal oxide layered structure and methods of forming the same
Some embodiment structures and methods are described. A structure includes an integrated circuit die at least laterally encapsulated by an encapsulant, and a redistribution structure on the integrated circuit die and encapsulant. The redistribution structure is electrically coupled to the integrated circuit die. The redistribution structure includes a first dielectric layer on at least the encapsulant, a metallization pattern on the first dielectric layer, a metal oxide layered structure on the metallization pattern, and a second dielectric layer on the first dielectric layer and the metallization pattern. The metal oxide layered structure includes a metal oxide layer having a ratio of metal atoms to oxygen atoms that is substantially 1:1, and a thickness of the metal oxide layered structure is at least 50 Å. The second dielectric layer is a photo-sensitive material. The metal oxide layered structure is disposed between the metallization pattern and the second dielectric layer.
1 . A semiconductor device comprising:
an integrated circuit die;
an encapsulant at least laterally encapsulating the integrated circuit die;
a through via extending from a first side of the encapsulant to a second side of the encapsulant;
a metallization pattern over the encapsulant;
an adhesion layer in physical contact with the metallization pattern, the adhesion layer comprising a metal oxide layer having a ratio of metal atoms to oxygen atoms that is substantially 1:1, the metal oxide layer extending throughout the adhesion layer, wherein the metal oxide layer comprises tungsten;
a dielectric material in physical contact with a top surface of the adhesion layer, the dielectric material continuously extending to be over a second metallization pattern; and
a package component electrically connected to the through via.
2 . The semiconductor device of claim 1 , wherein the package component comprises:
an integrated circuit die flip-chip; and
an interposer attached to the integrated circuit die flip-chip.
3 . The semiconductor device of claim 2 , wherein the integrated circuit die flip-chip is a logic die.
4 . The semiconductor device of claim 2 , wherein the integrated circuit die flip-chip is a memory die.
5 . The semiconductor device of claim 1 , further comprising an underfill material adjacent to the package component.
6 . The semiconductor device of claim 1 , wherein the package component is electrically connected to the through via using a solder material.
7 . A semiconductor device comprising:
an integrated circuit die:
a through via laterally removed from the integrated circuit die;
an encapsulant in physical contact with both the integrated circuit die and the through via;
a metallization layer over the integrated circuit die and the encapsulant, the metallization layer comprising:
a metallization pattern;
a metal oxide on the metallization pattern, the metal oxide having a ratio of metal atoms to oxygen atoms that is substantially 1:1, wherein the metal oxide comprises aluminum, a thickness of the metal oxide being at least 50 Å; and
a dielectric layer surrounding the metallization pattern and the metal oxide, at least part of the dielectric layer being a photo-sensitive material, the metal oxide being in physical contact with both the metallization pattern and a portion of the dielectric layer; and
a package component located on an opposite side of the encapsulant from the metallization layer, the package component electrically connected to the through via.
8 . The semiconductor device of claim 7 , wherein the package component is electrically connected to the through via using solder balls.
9 . The semiconductor device of claim 7 , wherein the package component comprises a memory die.
10 . The semiconductor device of claim 7 , further comprising an underfill material located adjacent to the package component.
11 . The semiconductor device of claim 7 , wherein the package component is electrically connected to the through via using metal pillars.
12 . The semiconductor device of claim 7 , wherein the package component comprises a logic die.
13 . A semiconductor device comprising:
a through via extending from a first side of an encapsulant to a second side of the encapsulant opposite the first side;
a semiconductor die within the encapsulant;
a first redistribution layer adjacent to the first side and in electrical connection with the through via, the first redistribution layer comprising a first metal oxide layer comprising a first metal oxide with a first ratio of first metal atoms and a first thickness of at least 50 Å;
a second redistribution layer adjacent to the second side and in electrical connection with the through via, the second redistribution layer comprising a second metal oxide layer with a second thickness of at least 50 Å, the second metal oxide layer comprising a second metal oxide with a second ratio of second metal atoms to oxygen atoms that is substantially 1:1, the second metal atoms comprising tungsten; and
a package component electrically connected to the through via, the package component comprising an integrated circuit die flip-chip attached to an interposer.
14 . The semiconductor device of claim 13 , wherein the first metal atoms comprise titanium, the first ratio of first metal atoms to oxygen atoms being substantially 1:1.
15 . The semiconductor device of claim 13 , wherein the first metal atoms comprise cobalt.
16 . The semiconductor device of claim 13 , wherein the first metal atoms comprise nickel.
17 . The semiconductor device of claim 13 , wherein the first ratio is between about 0.8:1 to 1.2:1.
18 . The semiconductor device of claim 13 , wherein the first ratio is between about 0.9:1 to 1.1:1.
19 . The semiconductor device of claim 13 , wherein the integrated circuit die flip-chip is a memory die.
20 . The semiconductor device of claim 13 , wherein the integrated circuit die flip-chip is a logic die.