Self-aligned interconnect with protection layer
An integrated circuit structure includes a first Inter-Layer Dielectric (ILD), a gate stack in the first ILD, a second ILD over the first ILD, a contact plug in the second ILD, and a dielectric protection layer on opposite sides of, and in contact with, the contact plug. The contact plug and the dielectric protection layer are in the second ILD. A dielectric capping layer is over and in contact with the contact plug.
1 . A method, comprising:
forming a first inter-layer dielectric over a semiconductor substrate and adjacent to a plurality of gate stacks, gate spacers being on sidewalls of the gate stacks;
forming an etch stop layer over the first ILD;
forming a second ILD over the etch stop layer;
etching the second ILD and the etch stop layer to form a first contact opening, wherein the first contact opening exposes the first ILD and at least one of the gate spacers;
forming a dielectric liner on sidewalls within the first contact opening;
forming a first contact plug within the first contact opening, wherein the first contact plug is between opposite portions of the dielectric liner;
etching the first contact plug to form a recess;
depositing a dielectric capping layer within the recess over and in contact with the first contact plug, the dielectric capping layer contacting the opposite portions of the dielectric liner;
depositing a third ILD over the second ILD;
forming a second contact opening through the third ILD to expose the dielectric capping layer and the first contact plug;
filling the second contact opening to form a second contact plug;
forming a third contact plug through the third ILD, the second ILD, and the etch stop layer.
2 . The method of claim 1 , wherein the dielectric liner comprises a material selected from the group consisting of silicon nitride, silicon oxynitride, and silicon carbo-nitride.
3 . The method of claim 1 , further comprising:
before depositing the second ILD, forming an etch stop layer over the first ILD, the etch stop layer comprising a material selected from the group consisting of silicon carbide, silicon oxynitride, and silicon carbo-nitride.
4 . The method of claim 1 , wherein the second contact opening is formed using an etching process with an etching selectivity that etches the third ILD faster than the dielectric capping layer and the dielectric liner.
5 . The method of claim 1 , wherein the second contact plug is electrically coupled to a gate electrode of one of the gate stacks.
6 . The method of claim 1 , wherein the dielectric capping layer is formed to a thickness that is greater than the thickness of the dielectric liner.
7 . The method of claim 1 , wherein the second contact plug comprises copper and further comprises forming a diffusion barrier layer lining the second contact opening before filling with copper.
8 . The method of claim 1 , wherein the second contact plug is electrically coupled to a source/drain region in the semiconductor substrate.
9 . The method of claim 1 , further comprising forming shallow trench isolation (STI) regions in the semiconductor substrate before forming the first ILD.
10 . The method of claim 1 , wherein the third contact plug is electrically coupled to one of the plurality of gate stacks.
11 . The method of claim 1 , wherein the third contact plug is electrically coupled to a source/drain region.
12 . A method, comprising:
forming a plurality of gate stacks with gate spacers on sidewalls of the gate stacks over a semiconductor substrate;
forming source/drain regions in the semiconductor substrate adjacent to the gate stacks;
depositing a first inter-layer dielectric over the semiconductor substrate to surround the gate stacks and gate spacers;
forming first contacts in the first ILD, the first contacts being electrically coupled to the source/drain regions;
depositing an etch stop layer over the first ILD;
depositing a second ILD over the etch stop layer;
patterning the second ILD to define a plurality of contact openings, each contact opening exposing a portion of the etch stop layer;
etching the exposed etch stop layer to expose the first ILD within the contact openings;
forming a dielectric protection layer on sidewalls of the contact openings;
filling the contact openings with a conductive material to form second contacts in electrical contact with the first contacts;
depositing a third ILD over the second ILD and the second contacts;
planarizing the third ILD to expose top surfaces of the second contacts;
forming a dielectric capping layer over the second contacts; and
forming third contacts in the third ILD, the third contacts being electrically connected to the second contacts and physically contacting the dielectric protection layer, wherein one of the third contacts extends through the third ILD, the second ILD, and the etch stop layer to be electrically coupled to one of the plurality of gate stacks.
13 . The method of claim 12 , wherein the second contacts are formed to be coplanar with a top surface of the second ILD.
14 . The method of claim 12 , wherein the dielectric capping layer is planarized to be level with a top surface of the third ILD.
15 . The method of claim 12 , further comprising forming silicide regions on the source/drain regions before depositing the first ILD.
16 . A method comprising:
forming a plurality of gate stacks on a semiconductor substrate, each gate stack having gate spacers on sidewalls of the gate stacks;
forming source/drain regions formed in the semiconductor substrate adjacent to the gate stacks;
forming a first inter-layer dielectric (ILD) layer over the semiconductor substrate and the source/drain regions and surrounding the gate stacks and gate spacers;
forming source/drain contact plugs in the first ILD layer and electrically connected to the source/drain regions;
forming an etch stop layer over the first ILD layer, the plurality of gate stacks, and the source/drain contact plugs;
forming a second ILD layer over the etch stop layer;
forming second contact plugs in the second ILD and the etch stop layer, the second contact plugs contacting the source/drain contact plugs;
forming a dielectric protection layer on sidewalls of the second contact plugs within the second ILD layer, the dielectric protection layer contacting at least one of the gate spacers;
forming a dielectric capping layer over and in contact with the source/drain contact plugs, wherein the dielectric capping layer has a top surface level with a top surface of the second ILD layer;
forming a third ILD over the second ILD and the second contact plugs; and
forming a fourth contact plug extending through the third ILD, the second ILD, and the etch stop layer to be electrically coupled to one of the source/drain contact plugs.
17 . The method of claim 16 , wherein the gate stacks comprise a high-k dielectric material and a metal gate electrode.
18 . The method of claim 16 further comprising:
forming gate contact plugs in the second ILD and electrically coupled with the gate stacks.
19 . The method of claim 16 , wherein the dielectric protection layer comprises a material having a material with an etching selectivity that is different from the etching selectivity of the second ILD layer.
20 . The method of claim 16 further comprising:
forming a third contact plug in the third ILD and physically contacting one of the second contact plugs and the dielectric protection layer.