Transistor cells including a deep via lined with a dielectric material
A transistor cell including a deep via that is at least partially lined with a dielectric material. The deep via may extend down to a substrate over which the transistor is disposed. The deep via may be directly connected to a terminal of the transistor, such as the source or drain, to interconnect the transistor with an interconnect metallization level disposed in the substrate under the transistor, or on at opposite side of the substrate as the transistor. Parasitic capacitance associated with the close proximity of the deep via metallization to one or more terminals of the transistor may be reduced by lining at least a portion of the deep via sidewall with dielectric material, partially necking the deep via metallization in a region adjacent to the transistor.
1 . A method of fabricating a transistor structure, the method comprising:
forming a source and a drain separated by a channel;
forming a gate electrode over the channel, wherein the source and drain are separated from the gate electrode by at least a spacer comprising a dielectric material;
forming a via opening that exposes the spacer along a sidewall of the via opening;
forming a liner within the via opening and in direct contact with the spacer, wherein the liner comprises a dielectric material;
depositing a conductive material within the via opening to interconnect a first end of a via metallization with the source or drain; and
forming a back-side metallization in contact with a second end of the via metallization, opposite the first end.
2 . The method of claim 1 , wherein forming the liner further comprises:
depositing a dielectric material on a sidewall of the via opening; and
recessing the dielectric material to a height below a top of the via opening.
3 . The method of claim 2 , further comprising forming an isolation dielectric and wherein forming the via opening comprises etching through at least a partial thickness of the isolation dielectric.
4 . The method of claim 3 , wherein the liner within the via opening covers at least the spacer.
5 . The method of claim 4 , wherein forming the liner further comprises depositing a material on the spacer selectively to the isolation dielectric.
6 . The method of claim 5 , wherein depositing the material on the spacer selectively further comprises depositing a silicon layer on the spacer; and
the method further comprises converting the silicon layer into a dielectric through oxidation or nitridation.
7 . The method of claim 5 , wherein forming the liner further comprises:
backfilling a bottom portion of the via opening with a sacrificial material;
depositing a dielectric material over the sacrificial material and on a sidewall of a top portion of the via opening left unfilled by the sacrificial material;
anisotropically etching the dielectric material to expose the sacrificial material; and
removing the sacrificial material.
8 . The method of claim 4 , wherein the liner has a relative permittivity no more than that of the spacer.
9 . The method of claim 1 , wherein forming the back-side metallization further comprises:
removing or thinning a substrate material to expose the second end of the via metallization; and
depositing the back-side metallization in contact with the second end of the via metallization.
10 . The method of claim 1 , wherein depositing the conductive material with the via opening further comprises depositing one or more metals in the via opening and in contact with at least one of the source or drain.
11 . The method of claim 1 , further comprising forming source metallization and drain metallization in contact with the source and drain, and wherein depositing the conductive material within the via opening comprises depositing one or more metals in the via opening and in contact with at least one of the source metallization or drain metallization.
12 . A method of fabricating an integrated circuit (IC) structure, the method comprising:
forming one or more device strata including a field effect transistor (FET) comprising a semiconductor material body, wherein:
the semiconductor material body comprises a channel material and the FET comprises:
a source semiconductor and a drain semiconductor separated by the channel material; and
a gate electrode adjacent to the channel material and separated from the source semiconductor and the drain semiconductor by a dielectric spacer;
forming a via opening through a thickness of the device strata that is at least equal to a thickness of the semiconductor material body, the via opening exposing the dielectric spacer;
forming a dielectric liner along a sidewall of the via opening, and in direct contact with the dielectric spacer; and
forming via metallization within the via opening, the via metallization separated from the gate electrode by at least the dielectric liner and the dielectric spacer.
13 . The method of claim 12 , further comprising forming a back-side metallization in contact with the via metallization.
14 . The method of claim 13 , wherein forming the back-side metallization further comprises:
removing or thinning a substrate material to expose the via metallization; and
depositing the back-side metallization in contact with the via metallization.
15 . The method of claim 12 , wherein the dielectric liner has a relative permittivity no more than that of the dielectric spacer.
16 . A method of fabricating a field effect transistor (FET) structure, the method comprising:
forming a source and a drain separated by a channel adjacent to an isolation dielectric;
forming a gate stack over the channel, the gate stack including a gate electrode and a gate dielectric;
forming source and drain metallization in contact with corresponding ones of the source and drain, and separated from the gate electrode by at least a spacer comprising a dielectric;
forming a via opening in the isolation dielectric that exposes the spacer at a sidewall of the via opening;
forming a liner within the via opening that is in direct contact with the spacer, wherein the liner comprises a dielectric;
depositing a conductive material with the via opening to interconnect a first end of a via metallization with the source or drain; and
forming a back-side metallization in contact with a second end of the via metallization, opposite the first end.
17 . The method of claim 16 , wherein forming the liner further comprises depositing a material on the spacer selectively to the isolation dielectric.
18 . The method of claim 16 , wherein forming the back-side metallization further comprises:
removing or thinning a substrate material to expose the via metallization; and
depositing the back-side metallization in contact with the via metallization.
19 . The method of claim 16 , wherein forming the liner further comprises:
backfilling a bottom portion of the via opening with a sacrificial material;
depositing a dielectric material over the sacrificial material and on a sidewall of a top portion of the via opening left unfilled by the sacrificial material;
anisotropically etching the dielectric material to expose the sacrificial material; and
removing the sacrificial material.