Face-to-face dies with a void for enhanced inductor performance
In accordance with the disclosure, an inductor may be formed over a semiconductor substrate of one or both dies in a face-to-face die arrangement while reducing the parasitic capacitance between the inductor and the adjacent die. In disclosed embodiments, a semiconductor device may include a void (e.g., an air gap) between the inductor and the adjacent die to reduce the parasitic capacitance between the inductor and the adjacent die. The void may be formed in the die that includes the inductor and/or the adjacent die. In some respects, the void may be etched in interface layers (e.g., comprising bump pads and dielectric material) between the semiconductor dies, and may extend along the length of the inductor.
1 . A semiconductor device comprising:
a first semiconductor die having,
a semiconductor substrate, and
an inductor; and
a second semiconductor die having,
a semiconductor substrate, and
a voided region to reduce parasitic capacitance between the inductor and the semiconductor substrate of the second semiconductor die, the voided region comprising at least one floating conductive portion of at least one metallization layer of the second semiconductor die, the at least one floating conductive portion being electrically inert with respect to the inductor;
wherein the first semiconductor die is mounted face-to-face with the second semiconductor die;
wherein the inductor of the first semiconductor die is disposed between at least one metallization layer of the first semiconductor die and the semiconductor substrate of the second semiconductor die; and
wherein the voided region of the second semiconductor die is vertically overlapping the inductor of the first semiconductor die in a direction perpendicular to a face of the first semiconductor die and extends from an inter-die interface pad layer on a face of the second semiconductor die towards a backside of the second semiconductor die.
2 . The semiconductor device of claim 1 , wherein the at least one floating conductive portion is not configured to carry signal or power and is included to satisfy design rules of the second semiconductor die.
3 . The semiconductor device of claim 1 , wherein the inductor is in an interface region between the first semiconductor die and the second semiconductor die, the interface region formed on a metallization region of the second semiconductor die.
4 . The semiconductor device of claim 1 , wherein the inductor is completely disposed vertically over each metallization layer of the first semiconductor die and each metallization layer of the second semiconductor die in the direction perpendicular to the face of the first semiconductor die.
5 . The semiconductor device of claim 1 , wherein the at least one floating conductive portion of the at least one metallization layer includes a plurality of floating conductive portions of a plurality of metallization layers of the second semiconductor die, the plurality of floating conductive portions comprising fill material that is included to satisfy design rules and being electrically inert with respect to the inductor.
6 . The semiconductor device of claim 1 , wherein the first semiconductor die includes a second voided region comprising one or more second floating conductive portions of metallization layers, the one or more second floating conductive portions being fill material that is electrically inert with respect to the inductor, the second voided region vertically overlapping the inductor and the voided region in the direction perpendicular to the face of the first semiconductor die, the second voided region extending, in the direction, through each metallization layer of the first semiconductor die to reach a backside of the first semiconductor die.
7 . The semiconductor device of claim 1 , wherein the voided region is a region that does not include any circuit components, is electrically inert with respect to the inductor, and reduces parasitic capacitance between the inductor and semiconductor substrate of the second semiconductor die, the region extending from a metallization layer of the second semiconductor die through the semiconductor substrate to reach a backside of the second semiconductor die.
8 . The semiconductor device of claim 7 , wherein the region includes an air gap that starts at a surface of the inductor and the region extends vertically from the surface to reach at least partially through backside interface terminals of the second semiconductor die.
9 . The semiconductor device of claim 1 , wherein the inductor is not included in the second semiconductor die.
10 . A semiconductor device comprising:
a first semiconductor die having an inductor disposed between at least one metallization layer and a side of the first semiconductor die; and
a second semiconductor die having a voided region to reduce parasitic capacitance between the inductor and a semiconductor substrate of the second semiconductor die, the voided region comprising at least one floating conductive portion of at least one metallization layer of the second semiconductor die, the at least one floating conductive portion being electrically inert with respect to the inductor;
wherein the side of the first semiconductor die is mounted to a first side of the second semiconductor die; and
wherein the voided region of the second semiconductor die is vertically overlapping the inductor of the first semiconductor die in a direction perpendicular to a face of the first semiconductor die and extends from the first side towards a second side of the second semiconductor die.
11 . The semiconductor device of claim 10 , wherein the first semiconductor die is mounted face-to-face with the second semiconductor die.
12 . The semiconductor device of claim 10 , wherein the voided region comprises fill material extending from the first side of the second semiconductor die to the second side of the second semiconductor die.
13 . The semiconductor device of claim 10 , wherein the voided region extends through at least a portion of a metallization region of the second semiconductor die.
14 . The semiconductor device of claim 10 , wherein the voided region extends through at least a portion of the semiconductor substrate of the second semiconductor die.
15 . The semiconductor device of claim 10 , wherein the voided region extends at least partially through backside interface terminals of the second semiconductor die.
16 . A semiconductor device comprising:
a first semiconductor die having,
a metallization region, and
an inductor disposed over the metallization region; and
a second semiconductor die having a voided region to reduce parasitic capacitance between the inductor and a semiconductor substrate of the second semiconductor die, the voided region comprising at least one floating conductive portion of at least one metallization layer of the second semiconductor die, the at least one floating conductive portion being electrically inert with respect to the inductor; and
a bonding dielectric layer mechanically coupling the first semiconductor die to a first side of the second semiconductor die;
wherein the inductor of the first semiconductor die is disposed between the metallization region of the first semiconductor die and the second semiconductor die;
wherein the voided region of the second semiconductor die is vertically overlapping the inductor of the first semiconductor die in a direction perpendicular to a face of the first semiconductor die and extends from the bonding dielectric layer towards a second side of the second semiconductor die.
17 . The semiconductor device of claim 16 , further comprising inter-die interface pads formed in the bonding dielectric layer and communicatively coupling the first semiconductor die and the second semiconductor die.
18 . The semiconductor device of claim 16 , wherein the bonding dielectric layer is formed on the first semiconductor die.
19 . The semiconductor device of claim 16 , wherein the bonding dielectric layer is formed on the second semiconductor die.
20 . The semiconductor device of claim 16 , wherein the inductor is connected to phase-locked loop circuitry to generate at least one clock signal.