Integrated circuit structure and manufacturing method thereof
A method includes forming a source/drain contact over a source/drain region. An ion implantation process is performed to form a doped region in a top of the source/drain contact. After the ion implantation process is performed, an interlayer dielectric (ILD) layer is deposited to cover the doped region of the source/drain contact. The ILD layer is etched to form a via opening exposing the source/drain contact. A source/drain via is filled in the via opening.
1 . A method comprising:
forming a source/drain contact over a source/drain region;
performing an ion implantation process to form a doped region in a top of the source/drain contact;
after performing the ion implantation process, depositing an interlayer dielectric (ILD) layer to cover the doped region of the source/drain contact;
etching the ILD layer to form a via opening exposing the source/drain contact and comprising punching through a portion of the doped region of the source/drain contact; and
filling a source/drain via in the via opening.
2 . The method of claim 1 , further comprising performing an annealing process after performing the ion implantation process.
3 . The method of claim 2 , wherein the annealing process is performed prior to forming the ILD layer.
4 . The method of claim 1 , wherein a dopant concentration of the doped region decreases as a distance from a top surface of the doped region increases.
5 . The method of claim 1 , wherein the top of the source/drain contact is doped with oxygen ions.
6 . The method of claim 1 , wherein the top of the source/drain contact is doped with germanium, argon, xenon, and/or boron.
7 . The method of claim 1 , further comprising:
depositing a middle contact etch stop layer to cover the doped region of the source/drain contact prior to depositing the ILD layer.
8 . A method comprising:
forming a gate structure over a substrate;
forming a dielectric cap over the gate structure;
forming a first source/drain contact and a second source/drain contact over the substrate and on opposite sides of the gate structure;
forming a first doped region in a top of the first source/drain contact;
forming a second doped region in a top of the dielectric cap;
depositing an interlayer dielectric (ILD) layer to cover the first doped region of the first source/drain contact; and
forming a source/drain via in the ILD layer and electrically connected to the first source/drain contact.
9 . The method of claim 8 , further comprising:
etching a portion of the first doped region of the first source/drain contact after depositing the ILD layer.
10 . The method of claim 8 , further comprising:
depositing a middle contact etch stop layer to cover the first doped region of the first source/drain contact prior to depositing the ILD layer.
11 . The method of claim 8 , wherein a dopant depth of the first doped region is in a range from about 1 Angstroms to about 50 Angstroms.
12 . The method of claim 8 , wherein dopants of the first doped region of the first source/drain contact are oxygen.
13 . The method of claim 8 , wherein the second doped region of the dielectric cap is in contact with the first doped region of the first source/drain contact.
14 . The method of claim 8 , wherein a ratio of a depth of the second doped region to a maximal thickness of the dielectric cap is in a range from about 3% to about 60%.
15 . A method comprising:
forming a gate structure over a substrate;
forming a first source/drain contact and a second source/drain contact over the substrate and on opposite sides of the gate structure;
performing an implantation process to the first source/drain contact to form a doped region in the first source/drain contact, wherein an undoped region of the first source/drain contact is between the doped region and the substrate after performing the implantation process;
depositing an interlayer dielectric (ILD) layer to cover the doped region of the first source/drain contact;
performing an etching process to form an opening in the ILD layer and expose the doped region; and
forming a source/drain via in the opening and connected to the first source/drain contact, wherein the source/drain via is in contact with the doped region and the undoped region of the first source/drain contact.
16 . The method of claim 15 , wherein performing the etching process is further to etch a portion of the doped region of the first source/drain contact.
17 . The method of claim 15 , wherein the doped region of the first source/drain contact is thinner than the undoped region of the first source/drain contact.
18 . The method of claim 15 , wherein the doped region of the first source/drain contact comprises oxygen.
19 . The method of claim 15 , wherein a bottom surface of the source/drain via is lower than a top surface of the doped region of the first source/drain contact.
20 . The method of claim 15 , further comprising depositing a middle contact etch stop layer to cover the doped region of the first source/drain contact prior to depositing the ILD layer.