Interconnect structure pattern
The present disclosure describes a structure with a substrate, a circuit element, a first metallization layer, and a second metallization layer. The circuit element is formed on the substrate. The first metallization layer is disposed over the substrate and includes a first metal line electrically connected to the circuit element and first dummy metal lines extending along a first direction. The second metallization layer is disposed directly above the first metallization layer and includes a second metal line electrically connected to the first metal line and second dummy metal lines extending along a second direction. The second direction is perpendicular to the first direction.
1 . A semiconductor structure, comprising:
a substrate including a circuit element formed thereon;
a first metallization layer disposed over the substrate and comprising:
a first metal line electrically connected to the circuit element; and
a plurality of first dummy metal lines extending along a first direction and electrically isolated from the first metal line; and
a second metallization layer disposed directly above the first metallization layer and comprising:
a second metal line electrically connected to the first metal line; and
a plurality of second dummy metal lines directly above the plurality of first dummy metal lines, extending along a second direction, and electrically isolated from the first metal line, the second metal line, and the plurality of first dummy metal lines, wherein one or more of the plurality of second dummy metal lines comprise a concave portion, a void structure, or combinations thereof, and wherein the second direction is perpendicular to the first direction.
2 . The semiconductor structure of claim 1 , wherein an elongated side of the first metal line extends along the first direction and an elongated side of the second metal line extends along the second direction.
3 . The semiconductor structure of claim 1 , wherein a dummy metal line and an other dummy metal line of the plurality of first dummy metal lines are offset with respect to one another along the first direction.
4 . The semiconductor structure of claim 3 , wherein the offset is less than a length of the dummy metal line along the first direction.
5 . The semiconductor structure of claim 1 , wherein the first direction is in a direction along a non-zero angle relative to a horizontal direction.
6 . The semiconductor structure of claim 1 , wherein an elongated side of the first metal line extends along the second direction and an elongated side of the second metal line extends along the first direction.
7 . The semiconductor structure of claim 1 , wherein the first metallization layer further comprises an other plurality of first dummy metal lines extending along the second direction.
8 . The semiconductor structure of claim 1 , wherein a dummy metal line of the plurality of first dummy metal lines and an other dummy metal line of the plurality of first dummy metal lines have different widths.
9 . A semiconductor structure, comprising:
a substrate including a circuit element formed thereon;
a first metallization layer disposed over the substrate and comprising:
a first metal line electrically connected to the circuit element; and
a plurality of first dummy metal lines extending along a first direction and electrically isolated from the first metal line, wherein one or more of the plurality of first dummy metal lines comprise a concave portion, a void structure, or combinations thereof; and
a second metallization layer disposed directly above the first metallization layer and comprising:
a second metal line electrically connected to the first metal line; and
a plurality of second dummy metal lines directly above the plurality of first dummy metal lines, extending along a second direction, and electrically isolated from the second metal line and the plurality of first dummy metal lines, wherein one or more of the plurality of second dummy metal lines comprise the concave portion, the void structure, or combinations thereof, and wherein the second direction is perpendicular to the first direction.
10 . The semiconductor structure of claim 9 , wherein a length of an elongated side of the plurality of first dummy metal lines and a length of an elongated side of the plurality of second dummy metal lines is greater than a length of an elongated side of the first metal line and a length of an elongated side of the second metal line, respectively.
11 . The semiconductor structure of claim 9 , wherein a length of an elongated side of the plurality of first dummy metal lines and a length of an elongated side of the plurality of second dummy metal lines is less than a length of an elongated side of the first metal line and a length of an elongated side of the second metal line, respectively.
12 . The semiconductor structure of claim 9 , wherein the void structure comprises a dielectric material or air.
13 . A method, comprising:
forming a circuit element on a substrate;
forming first metal lines over the substrate and electrically connected to the circuit element;
forming second metal lines directly above the first metal lines and electrically connected to the first metal lines;
forming, between the first metal lines, a plurality of first dummy metal lines that extend along a first direction; and
forming, between the second metal lines, a plurality of second dummy metal lines that extend along a second direction perpendicular to the first direction, wherein the plurality of second dummy metal lines are directly above and isolated from the plurality of first dummy metal lines, wherein one or more of the plurality of second dummy metal lines comprise a concave portion, a void structure, or combinations thereof.
14 . The method of claim 13 , further comprising forming additional dummy metal lines between the first metal lines and the plurality of first dummy metal lines, between the second metal lines and the plurality of second dummy metal lines, or combinations thereof.
15 . The method of claim 13 , wherein forming the circuit element comprises forming a transistor device, a capacitor, or combinations thereof on the substrate.
16 . The method of claim 13 , wherein forming the first metal lines comprises routing the first metal lines with a spacing between two or more of the first metal lines.
17 . The method of claim 16 , wherein forming the plurality of first dummy metal lines comprises forming the plurality of first dummy metal lines in the spacing.
18 . The method of claim 14 , wherein forming the second metal lines comprises routing the second metal lines with a spacing between two or more of the second metal lines.
19 . The method of claim 18 , wherein forming the plurality of second dummy metal lines comprises forming the plurality of second dummy metal lines in the spacing.
20 . The method of claim 13 , wherein forming the plurality of first dummy metal lines and the plurality of second dummy metal lines comprises forming the plurality of first dummy metal lines with an elongated side perpendicular to an elongated side of the plurality of second dummy metal lines.