Solid-state imaging apparatus, manufacturing method thereof, and electronic equipment
The present disclosure relates to a solid-state imaging apparatus, a manufacturing method thereof, and electronic equipment that are able to suppress nonuniform reflection of incident light. The solid-state imaging apparatus includes an imaging element chip and a device chip. The imaging element chip has a semiconductor substrate. The device chip is bonded to a wiring layer opposite the light incident surface of the semiconductor substrate. The device chip is disposed in a pixel region of the imaging element chip. The wiring layer of the imaging element chip includes a dummy metal wiring in a region where the device chip of the pixel region is not disposed. The technology according to the present disclosure is applicable, for example, to the solid-state imaging apparatus that is formed by bonding the imaging element chip to the device chip.
1 . A solid-state imaging apparatus, comprising:
an imaging element chip that includes a first semiconductor substrate;
a wiring layer opposite to a light incident surface of the first semiconductor substrate, wherein the wiring layer includes a dummy metal wiring and a metal wiring; and
a first device chip bonded to the wiring layer, wherein
the first device chip is in a pixel region of the imaging element chip, and
the dummy metal wiring is in a region where the first device chip of the pixel region is not disposed.
2 . The solid-state imaging apparatus according to claim 1 , wherein the dummy metal wiring is in a same layer as the metal wiring in a region where the first device chip in the pixel region is disposed.
3 . The solid-state imaging apparatus according to claim 2 , wherein
the metal wiring of the pixel region includes a connection wiring and the dummy metal wiring,
the connection wiring is configured to transmit and receive power or signals to and from the wiring layer of the first device chip, and
the dummy metal wiring is configured to not transmit and receive the power or the signals.
4 . The solid-state imaging apparatus according to claim 2 , wherein
the dummy metal wiring is in a whole region where the first device chip of the pixel region is not disposed, and
the dummy metal wiring is of a same plane size and a same pitch as the metal wiring.
5 . The solid-state imaging apparatus according to claim 2 , wherein percentage of area occupied by the dummy metal wiring in a first region where the first device chip of the pixel region is not disposed is equivalent to percentage of area occupied by the metal wiring in a second region where the first device chip of the pixel region is disposed.
6 . The solid-state imaging apparatus according to claim 2 , wherein the dummy metal wiring and the metal wiring are in a layer that is away from bonding surfaces between the imaging element chip and the first device chip and toward the first semiconductor substrate.
7 . The solid-state imaging apparatus according to claim 6 , wherein the bonding surfaces between the imaging element chip and the first device chip are connected by metal bonding.
8 . The solid-state imaging apparatus according to claim 2 , wherein
the wiring layer further includes a stopper film that is on surfaces of the dummy metal wiring and the metal wiring, and
the stopper film is toward the first semiconductor substrate.
9 . The solid-state imaging apparatus according to claim 1 , wherein
a plurality of device chips are bonded to the wiring layer of the first semiconductor substrate, and
the plurality of device chips includes the first device chip.
10 . The solid-state imaging apparatus according to claim 2 , further comprising a plurality of device chips, wherein
the plurality of device chips is of different types,
the plurality of device chips includes the first device chip, and
the plurality of device chips is additionally bonded to a peripheral region outside the pixel region of the imaging element chip.
11 . The solid-state imaging apparatus according to claim 10 , wherein the wiring layer of the imaging element chip includes the dummy metal wiring in a region where the first device chip of the peripheral region is not disposed.
12 . The solid-state imaging apparatus according to claim 11 , wherein the dummy metal wiring of the peripheral region is of a same plane size and a same pitch as the dummy metal wiring of the pixel region.
13 . The solid-state imaging apparatus according to claim 11 , wherein percentage of area occupied by the dummy metal wiring in a region where the first device chip of the peripheral region is not disposed is equivalent to percentage of area occupied by the metal wiring in a region where the first device chip of the peripheral region is disposed.
14 . The solid-state imaging apparatus according to claim 1 , wherein
the imaging element chip further includes two or more semiconductor substrates in a stacked configuration, and
the two or more semiconductor substrates include the first semiconductor substrate.
15 . A manufacturing method of a solid-state imaging apparatus, the manufacturing method comprising:
bonding a device chip to a pixel region of a wiring layer opposite a light incident surface of a semiconductor substrate for an imaging element chip; and
forming a dummy metal wiring in a region where the device chip of the pixel region is not disposed, wherein the wiring layer includes the dummy metal wiring and a metal wiring.
16 . An electronic equipment, comprising:
a solid-state imaging apparatus that includes an imaging element chip, a wiring layer, and a device chip, wherein
the imaging element chip includes a semiconductor substrate,
the wiring layer is opposite to a light incident surface of the semiconductor substrate,
the wiring layer includes a dummy metal wiring and a metal wiring,
the device chip is bonded to the wiring layer,
the device chip is in a pixel region of the imaging element chip, and
the dummy metal wiring is in a region where the device chip of the pixel region is not disposed.