Wide band gap semiconductor device with surface insulating film
A semiconductor device of the present invention includes a semiconductor layer of a first conductivity type having a cell portion and an outer peripheral portion disposed around the cell portion, and a surface insulating film disposed in a manner extending across the cell portion and the outer peripheral portion, and in the cell portion, formed to be thinner than a part in the outer peripheral portion.
1 . A semiconductor device including a MISFET (Metal Insulator Field Effect Transistor), the semiconductor device comprising:
a semiconductor layer made of SiC, the semiconductor layer having a cell portion including a plurality of unit cells, an outer peripheral portion arranged around the cell portion, a base surface, and a lower surface formed at a relatively low height position with respect to the base surface;
a gate electrode provided on the semiconductor layer via a gate insulating film;
a gate pad;
a first surface insulating film formed on a surface of the semiconductor layer in the cell portion, the first surface insulating film covering the gate electrode and exposing a source portion including the lower surface through a contact hole;
a second surface insulating film formed on the surface of the semiconductor layer in the outer peripheral portion; and
a source pad formed on the first surface insulating film and electrically connected to the source portion through the contact hole, wherein the source pad has a step caused by a level difference between a surface of the first surface insulating film and the lower surface of the source portion, and
a thickness of the first surface insulating film is smaller than a thickness of the second surface insulating film.
2 . The semiconductor device according to claim 1 , further comprising:
a source region of a first conductivity type provided on the surface of the semiconductor layer;
a channel region of a second conductivity type which is provided in a manner contacting the source region and in which a channel is formed at ON-time.
3 . The semiconductor device according to claim 1 , wherein the gate insulating film includes SiO 2 .
4 . The semiconductor device according to claim 1 , wherein the plurality of unit cells in a striped shape are formed in the cell portion.
5 . The semiconductor device according to claim 2 , further comprising a drain region of a first conductivity type provided in a manner contacting the channel region.
6 . The semiconductor device according to claim 1 , wherein the gate electrode is a planar structure.
7 . The semiconductor device according to claim 1 , further comprising a gate trench formed on a surface side of the cell portion, wherein
the gate electrode is buried in the gate trench via the gate insulating film, and
the semiconductor device further comprises a voltage resistant structure having a semiconductor region.
8 . The semiconductor device according to claim 7 , wherein the gate trench includes a line-shaped trench.
9 . The semiconductor device according to claim 8 , wherein the gate insulating film includes at least one of SiO 2 , AlON, Al 2 O 3 , SiO 2 /AlON, SiO 2 /AlON/SiO 2 , SiO 2 /SiN and SiO 2 /SiN/SiO 2 .
10 . The semiconductor device according to claim 7 , wherein the gate insulating film is, at a bottom portion of the gate trench, formed to be thicker than a part at a side portion of the gate trench.
11 . The semiconductor device according to claim 1 , further comprising a source electrode that includes Al or Cu.
12 . The semiconductor device according to claim 1 , wherein at least one of the unit cells includes:
an n-type source region formed in a surface portion of the semiconductor layer;
a p-type channel region facing the gate electrode via the gate insulating film;
a channel contact region disposed in a region separated from the p-type channel region; and
a p-type layer electrically connecting the p-type channel region and the channel contact region.
13 . The semiconductor device according to claim 12 , wherein
the at least one of the unit cells has a recess forming the lower surface, the recess being formed in the surface of the semiconductor layer in a region surrounded by the n-type source region,
the p-type layer is formed below the recess, and
the channel contact region is formed, at a bottom of the recess, in a surface portion of the p-type layer.
14 . The semiconductor device according to claim 13 , wherein the second surface insulating film has a thickness of 5500 Å to 20000 Å.
15 . The semiconductor device according to claim 14 , wherein a trench-gate-type MISFET is formed in the cell portion.
16 . The semiconductor device according to claim 14 , wherein a planar-gate-type MISFET is formed in the cell portion.
17 . The semiconductor device according to claim 14 , wherein the unit cells of the cell portion are regularly arranged in a polygonal shape or a stripe shape in a plan view.
18 . The semiconductor device according to claim 14 , wherein a multilayer wiring structure is disposed on the first surface insulating film.