IP Library › Assignment 012287/0780
Patent Assignment
Reel/Frame 012287/0780

Assignment of Assignor's Interest

Recorded: 2001-06-22 Pages: 31
Assignor
LOCKHEED MARTIN CORPORATION
Executed: 2000-11-27
Assignee
BAE SYSTEMS INFORMATION AND ELECTRONIC SYSTEMS INTEGRATION, INC.
P.O. BOX 868, NHQ1-719, NASHUA, NEW HAMPSHIRE, 03061
Covered Properties (82)
Fet Read Only Memory Cell with Word Line Augmented Precharging of the Bit Lines
Patent: 4,725,986 →
Application: 06/534,035 →
High Density, High Performance, Single Event Upset Immune Data Storage Cell
Patent: 4,797,804 →
Application: 07/023,426 →
Parity Generator Circuit and Method
Patent: 4,879,675 →
Application: 07/156,626 →
Soft Error Resistant Data Storage Cells
Patent: 4,852,060 →
Application: 07/176,052 →
Zero Standby Power, Radiation Hardened, Memory Redundancy Circuit
Patent: 4,996,670 →
Application: 07/414,889 →
Cmos Off Chip Driver for Fault Tolerant Cold Sparing
Patent: 5,117,129 →
Application: 07/598,300 →
Small Cell, Low Contact Assistance Rugged Power Field Effect Devices and Method of Fabrication
Patent: 5,234,851 →
Application: 07/829,667 →
Distributed Programmable Priority Arbitration
Patent: 5,307,466 →
Application: 07/876,239 →
Fast Fourier Transform Using Balanced Coefficients
Patent: 5,365,469 →
Application: 08/004,217 →
Method of Forming a Frontside Contact to the Silicon Substrate of a Soi Wafer
Patent: 5,314,841 →
Application: 08/054,992 →
Method of Making Gate Overlapped Lightly Doped Drain for Buried Channel Devices
Patent: 5,358,879 →
Application: 08/054,994 →
Power Bus Digital Communication System
Patent: 5,644,286 →
Application: 08/131,346 →
Method to Radiation Harden the Buried Oxide in Silicon-on-Insulator Structures
Patent: 5,360,752 →
Application: 08/142,030 →
Spare Signal Line Switching Method and Apparatus
Patent: 5,448,572 →
Application: 08/212,372 →
Method to Prevent Latch-Up and Improve Breakdown Voltage in Soi Mosfets
Patent: 5,527,724 →
Application: 08/304,639 →
Current Overload Protection Circuit
Patent: 5,457,591 →
Application: 08/371,718 →
Single Event Upset Hardened Cmos Latch Circuit
Patent: 5,504,703 →
Application: 08/382,112 →
Magnification Correction for 1-X Proximity X-Ray Lithography
Patent: 5,504,793 →
Application: 08/389,993 →
Single Event Upset Immune Register with Fast Write Access
Patent: 5,525,923 →
Application: 08/391,798 →
Efficient Fault Tolerant Switching Circuit for Redundant D.C. Power Supplies
Patent: 5,598,041 →
Application: 08/559,584 →
Error Detection and Fault Isolation for Lockstep Processor Systems
Patent: 5,915,082 →
Application: 08/660,640 →
High Accuracy Fabrication of X-Ray Masks with Optical and E-Beam Lithography
Patent: 5,756,234 →
Application: 08/663,826 →
X-Ray Mask Pellicle
Patent: 5,793,836 →
Application: 08/716,657 →
Process to Personalize Master Slice Wafers and Fabricate High Density Vlsi Components with a Single Masking Step
Patent: 5,858,817 →
Application: 08/728,880 →
Fault Tolerant Mosfet Driver
Patent: 5,796,274 →
Application: 08/733,080 →
Lithographic Patterning Method and Mask Set Therefor with Light Field Trim Mask
Patent: 5,807,649 →
Application: 08/740,598 →
Electrostatic Discharge Protection for Silicon-On-Insulator
Patent: 6,034,399 →
Application: 08/812,183 →
Ring Domains for Bandwidth Sharing
Patent: 5,901,148 →
Application: 08/812,184 →
Secure Data Transmission on a Tdm Isochronous Network
Patent: 5,970,095 →
Application: 08/837,165 →
Digital Multi-Channel Demultiplexer/Multiplex (Mcd/M Architecture).
Patent: 5,867,479 →
Application: 08/884,650 →
Control and Telemetry Signal Communication System for Geostationary Satellites
Patent: 6,188,874 →
Application: 08/884,675 →
Reversible Keypad and Display for a Telephone Handset
Patent: 6,052,606 →
Application: 08/989,463 →
Integrated Circuit Package and Method Increasing Density of I/O Leads
Patent: 6,329,594 →
Application: 09/007,980 →
Multi-Channel Overvoltage Protection Circuit
Patent: 6,127,879 →
Application: 09/030,902 →
Digital Multi-Channel Demultiplexer/Multiplexer (Mcd/M) Architecture
Patent: 6,091,704 →
Application: 09/241,313 →
Pattern Density Tailoring for Etching of Advanced Lithographic Masks
Patent: 6,365,326 →
Application: 09/307,126 →
Memory Device Having a Chip Select Speedup Feature and Associated Methods
Patent: 6,169,702 →
Application: 09/320,207 →
Memory Device Having Reduced Power Requirements and Associated Methods
Patent: 6,181,641 →
Application: 09/320,227 →
Method and Apparatus for Evaluating a Known Good Die Using Both Wire Bond and Flip-Chip Interconnects
Patent: 6,221,682 →
Application: 09/321,565 →
Error Detection and Fault Isolation for Lockstep Processor Systems
Patent: 6,065,135 →
Application: 09/325,641 →
Radiation Hardened Six Transistor Random Access Memory and Memory Device
Patent: 6,111,780 →
Application: 09/325,645 →
Satellite Telephone Handset
Patent: 6,510,227 →
Application: 09/384,429 →
Publication: US 2002/0054677
Method and Apparatus for Hardening a Static Random Access Memory Cell from Single Event Upsets
Patent: 6,285,580 →
Application: 09/441,941 →
Single Event Upset (Seu) Hardened Static Random Access Memory Cell
Patent: 6,208,554 →
Application: 09/441,942 →
Single-Event Upset Hardened Reconfigurable Bi-Stable Cmos Latch
Patent: 6,369,630 →
Application: 09/449,723 →
Enhanced Single Event Upset Immune Latch Circuit
Patent: 6,275,080 →
Application: 09/480,454 →
Method for Fabricating Resistors Within Semiconductor Integrated Circuit Devices
Patent: 6,717,233 →
Application: 09/491,230 →
In Situ Proximity Gap Monitor for Lithography
Patent: 6,717,685 →
Application: 09/502,062 →
Self-restoring single event upset (seu) hardened multiport memory cell
Patent: 6,215,694 →
Application: 09/553,595 →
Method and Apparatus for a Single Event Upset (Seu) Tolerant Clock Splitter
Patent: 6,456,138 →
Application: 09/559,659 →
Method and Apparatus for a Scannable Hybrid Flip Flop
Patent: 6,629,276 →
Application: 09/559,660 →
Method and apparatus for a single even upset (SEU) tolerant clock splitter
Patent: 6,362,676 →
Application: 09/559,661 →
Method and Apparatus for a Voltage Responsive Reset for Eeprom
Patent: 6,418,056 →
Application: 09/563,197 →
Distributed Determination of Explicit Rate in an Atm Communication System
Patent: 6,885,637 →
Application: 09/570,050 →
Self-equalized low poer precharge sense amp for high speed srams
Patent: 6,301,179 →
Application: 09/570,064 →
Multiplexor having a single event upset (SEU) immune data keeper circuit
Patent: 6,282,140 →
Application: 09/589,732 →
Increasing the Susceptability of an Integrated Circuit to Ionizing Radiation
Patent: 6,794,733 →
Application: 09/590,805 →
Semiconductor Device and Circuit Having Low Tolerance to Ionizing Radiation
Patent: 6,441,440 →
Application: 09/590,806 →
Apparatus and method for manufacturing a semiconductor circuit
Application: 09/590,809 →
System and Method of Providing a Spread Spectrum Pulse Width Modulator Clock
Patent: 6,895,046 →
Application: 09/591,731 →
Circuit for limiting inrush current through a transistor
Patent: 6,225,797 →
Application: 09/591,958 →
Process for production of 1, 3-DI (2-p-hydroxyphenyl-2-propyl) benzene
Patent: 6,326,522 →
Application: 09/592,403 →
Tool Suite for the Rapid Development of Advanced Standard Cell Libraries
Patent: 6,539,533 →
Application: 09/597,229 →
Low -Power Cmos Device and Logic Gates/Circuits Therewith
Patent: 6,429,492 →
Application: 09/598,681 →
Method for Testing of Known Good Die
Patent: 6,697,978 →
Application: 09/624,247 →
Digital multi-channel demultiplexer/multiplexer (MCD/M) architecture
Patent: 6,351,451 →
Application: 09/625,641 →
Radiation Hardened Silicon-on-Insulator (Soi) Transistor Having a Body Contact
Patent: 6,399,989 →
Application: 09/630,216 →
Redundant Oscillator and Method for Generating a Regulated Signal
Patent: 6,640,311 →
Application: 09/636,125 →
Single event upset (SEU) hardened static random access memory cell
Patent: 6,259,643 →
Application: 09/651,155 →
Circuit for Filtering Single Event Effect (See) Induced Glitches
Patent: 6,392,474 →
Application: 09/651,156 →
Single Event Upset Immune Oscillator Circuit
Patent: 6,448,862 →
Application: 09/667,040 →
Dual Mode Telephone Handset
Patent: 414,486 →
Application: 29/069,642 →
Method to Harden Shallow Trench Isolation Against Total Ionizing Dose Radiation
Application: 60/146,895 →
Oscillator and Method for Generating a Frequency Within a Stable Frequency Range
Application: 60/163,757 →
Integrated resistor having aligned body and contact and method for forming the same
Application: 60/178,247 →
Polyphase-DFT sub-band definition filtering architecture
Application: 60/181,512 →
Method and apparatus for a radiation hardened clock splitter
Application: 60/200,348 →
Single event upset immune logic family
Application: 60/203,895 →
Novel CMOS SRAM cell design with prescribed power-on data state
Application: 60/220,700 →
Radiation tolerant storage array sense latch
Application: 60/224,648 →
SEU B-latch for power PLL phase-detector
Application: 60/224,649 →
Integrated circuits containing transistors operable with two power supply voltages
Application: 60/224,650 →
Related Assignments (16)
Other recorded transfers of the patents in this record — the chain of ownership.
Assignment of Assignor's Interest Jan 29, 2010
From: BAE SYSTEMS INFORMATION AND ELECTRONIC SYSTEMS INTEGRATION INC.
To: RETRO REFLECTIVE OPTICS
Reel/Frame 023870/0156 →
Assignment of Assignor's Interest Feb 5, 2010
From: BAE SYSTEMS INFORMATION AND ELECTRONIC SYSTEMS INTEGRATION INC.
To: RETRO REFLECTIVE OPTICS
Reel/Frame 023915/0043 →
Security Agreement Feb 8, 2010
From: RETRO REFLECTIVE OPTICS, LLC
To: CREDIT SUISSE MANAGEMENT LLC
Reel/Frame 023905/0580 →
Corrective Assignment to Correct the Assignee Name Should Read, "Retro Reflective Optics, Llc" Previously Recorded on Reel 023870 Frame 0156. Assignor(S) Hereby Confirms the Assignment of the Assignor's Interest. Mar 24, 2011
From: BAE SYSTEMS INFORMATION AND ELECTRONIC SYSTEMS INTEGRATION INC.
To: RETRO REFLECTIVE OPTICS, LLC
Reel/Frame 026010/0120 →
Assignment of Assignor's Interest Sep 13, 2011
From: RETRO REFLECTIVE OPTICS, LLC
To: LATERAL RESEARCH LIMITED LIABILITY COMPANY
Reel/Frame 026896/0001 →
Confirmatory Assignment Dec 14, 2011
From: HADDAD, NADIM F.
To: INTERNATIONAL BUSINESS MACHINES CORPORATION
Reel/Frame 027379/0748 →
Correction to the Recordation Cover Sheet of the Assignee Recorded at 008430/0312 on 12/23/1996 Dec 14, 2011
From: INTERNATIONAL BUSINESS MACHINES CORPORATION
To: LOCKHEED MARTIN FEDERAL SYSTEMS, INC.
Reel/Frame 027380/0841 →
Confirmatory Assignment of Patent Rights Dec 16, 2011
From: EDENFELD, ARTHUR
To: INTERNATIONAL BUSINESS MACHINES CORPORATION
Reel/Frame 027400/0820 →
Confirmatory Assignment Dec 20, 2011
From: BRADY, FREDERICK T.
To: INTERNATIONAL BUSINESS MACHINES CORPORATION
Reel/Frame 027415/0358 →
Assignment of Assignor's Interest Jan 8, 2012
From: BAE SYSTEMS INFORMATION AND ELECTRONIC SYSTEMS INTEGRATION, INC.
To: OAL DATA LIMITED LIABILITY COMPANY
Reel/Frame 027497/0554 →
Assignment of Assignor's Interest Jan 25, 2012
From: LOCKHEED MARTIN FEDERAL SYSTEMS, INC.
To: LOCKHEED MARTIN CORPORATION
Reel/Frame 027592/0303 →
Corrective Assignment to Correct the Conveying Assignor Previously Recorded on Reel 008732 Frame 0103. Assignor(S) Hereby Confirms the Assignor Is "Lockheed Martin Federal Systems, Inc.". Jan 25, 2012
From: LOCKHEED MARTIN FEDERAL SYSTEMS, INC.
To: LOCKHEED MARTIN CORPORATION
Reel/Frame 027595/0457 →
Corrective Assignment to Correct the Inventor Name "Nadium F. Haddad" Previously Recorded on Reel 006542 Frame 0707. Assignor(S) Hereby Confirms the Inventor Name Is "Nadim F. Haddad". Jan 25, 2012
From: BRADY, FREDERICK T.; HADDAD, NADIM F.
To: INTERNATIONAL BUSINESS MACHINES CORPORATION
Reel/Frame 027595/0852 →
Assignment of Assignor's Interest Jan 25, 2012
From: BRADY, FREDERICK T.; HADDAD, NADIM F.; EDENFELD, ARTHUR
To: INTERNATIONAL BUSINESS MACHINES CORPORATION
Reel/Frame 027592/0127 →
Partial Release of Security Interest Jul 11, 2012
From: CREDIT SUISSE MANAGEMENT LLC
To: RETRO REFLECTIVE OPTICS, LLC
Reel/Frame 028543/0350 →
Merger Jan 19, 2016
From: LATERAL RESEARCH LIMITED LIABILITY COMPANY
To: GULA CONSULTING LIMITED LIABILITY COMPANY
Reel/Frame 037526/0577 →