IP Library › Assignment 012428/0236
Patent Assignment
Reel/Frame 012428/0236

Security Agreement

Recorded: 2002-01-15 Pages: 43
Assignor
SILICON GRAPHICS, INC.
Executed: 2001-11-09
Assignee
FOOTHILL CAPITAL CORPORATION
SUITE 3000 WEST, 2450 COLORADO AVENUE, SANTA MONICA, CALIFORNIA, 90404
Covered Properties (372)
Instruction Cache Memory System
Patent: 4,442,488 →
Application: 06/468,506 →
Computer Vector Multiprocessing Control
Patent: 4,636,942 →
Application: 06/488,082 →
Direct-Execution Microprogrammable Microprocessor System
Patent: 4,761,733 →
Application: 06/710,615 →
System for Multiprocessor Communication Using Local and Common Semaphore and Information Registers
Patent: 4,754,398 →
Application: 06/750,487 →
Flexible Chaining in Vector Processor with Selective Use of Vector Registers as Operand and Result Registers
Patent: 4,661,900 →
Application: 06/858,862 →
Zif Edge Connector
Patent: 4,700,996 →
Application: 06/916,509 →
Data Modulation Interface
Patent: 4,771,440 →
Application: 06/937,374 →
Massively Parallel Vector Processing Computer
Patent: 4,891,751 →
Application: 07/031,697 →
Lead Bonding of Chips Onto Boards and Circuit Boards to Circuit Boards
Patent: 5,054,192 →
Application: 07/053,142 →
Gallium Arsenide Depletion Mode Mesfet Logic Cell
Patent: 4,965,863 →
Application: 07/104,758 →
Peripheral Interface System
Patent: 4,807,121 →
Application: 07/205,533 →
Computer Vector Multiprocessing Control with Multiple Access Memory and Priority Conflict Resolution Method
Patent: 4,901,230 →
Application: 07/208,809 →
Parallel Board Zif Module Connector
Patent: 4,911,645 →
Application: 07/284,905 →
Wire/Disk Board-to-Board Interconnect Device
Patent: 4,859,188 →
Application: 07/306,229 →
Method and Apparatus for Cooling an Integrated Circuit Chip During Testing
Patent: 4,982,153 →
Application: 07/307,259 →
System for Multiprocessor Communication
Patent: 5,526,487 →
Application: 07/308,401 →
Reduced Capacitance Chip Carrier
Patent: 5,134,247 →
Application: 07/313,395 →
Cam Actuated Electrical Connector
Patent: 4,975,074 →
Application: 07/315,124 →
Linear Nearest Neighbor Interconnect Bus System
Patent: 5,003,508 →
Application: 07/338,557 →
Twisted Wire Jumper Electrical Interconnector and Method of Mailing
Patent: 5,014,419 →
Application: 07/347,507 →
Two-Piece Edge Zif Connector with Sliding Block
Patent: 4,984,993 →
Application: 07/351,871 →
File Characterization for Computer Operating and File Management Systems
Patent: 5,226,163 →
Application: 07/389,836 →
Modular Input/Output System for Supercomputers
Patent: 5,347,637 →
Application: 07/390,722 →
Read-While-Write Ram Cell
Patent: 4,964,081 →
Application: 07/393,528 →
Retaining Means for Removable Computer Drive and Release Means for Same
Patent: 4,960,384 →
Application: 07/408,741 →
High Power, High Density Interconnect Method and Apparatus for Integrated Circuits
Patent: 5,127,986 →
Application: 07/444,747 →
Miniature Controlled-Impedance Transmission Line Cable and Method of Manufacture
Patent: 5,015,800 →
Application: 07/454,022 →
Cluster Architecture for a Highly Parallel Scalar/Vector Mulriprocessor System
Patent: 5,197,130 →
Application: 07/459,083 →
Air Jet Impingement on Miniature Pin-Fin Heat Sinks for Cooling Electronic Components
Patent: 5,083,194 →
Application: 07/465,042 →
Skew-Compensated Clock Distribution System
Patent: 5,258,660 →
Application: 07/465,947 →
Parallel Processing System for Matrix Calculation
Patent: 5,081,573 →
Application: 07/469,818 →
Method of Fabricating Metallized Chip Carriers Form Wafer-Shaped Substrates
Patent: 5,182,420 →
Application: 07/506,729 →
Method and Apparatus for Sharing Memory in a Multiprocessor System
Patent: 5,247,637 →
Application: 07/531,861 →
Method and Apparatus for Non-Sequential Resource Access
Patent: 5,208,914 →
Application: 07/535,786 →
Vertical Semiconductor Interconnection Method and Structure
Patent: 5,041,903 →
Application: 07/535,837 →
Control and Maintenance Subsystem Network for Use with a Multiprocessor Computer System
Patent: 5,253,359 →
Application: 07/535,901 →
Distributed Architecture for Input/Output for a Multiprocessor System
Patent: 5,168,547 →
Application: 07/536,182 →
Dedicated Centralized Signaling Mechanism for Selectively Signaling Devices in a Multiprocessor System
Patent: 5,239,629 →
Application: 07/536,192 →
Method and Apparatus for a Special Purpose Arithmetic Boolean Unit
Patent: 5,175,862 →
Application: 07/536,197 →
Global Registers for a Multiprocessor System
Patent: 5,165,038 →
Application: 07/536,198 →
Clock Distribution Apparatus and Processes Using Electrical and Optical Delay Lines Particularly Useful in Multiprocessor Systems
Patent: 5,293,626 →
Application: 07/536,270 →
Packaging Architecture for a Highly Parallel Multiprocessor System
Patent: 5,251,097 →
Application: 07/536,395 →
Scalar/Vector Processor
Patent: 5,430,884 →
Application: 07/536,409 →
Method and Apparatus for a Multiple Request Toggling Priority System
Patent: 5,168,570 →
Application: 07/536,417 →
System and Method for Controlling a Highly Parallel Multiprocessor Using an Anarchy Based Scheduler for Parallel Execution Thread Scheduling
Patent: 5,179,702 →
Application: 07/537,466 →
Flexible Automated Bonding Method and Apparatus
Patent: 5,127,570 →
Application: 07/545,271 →
Computer Signal Interconnect Apparatus
Patent: 5,144,691 →
Application: 07/556,031 →
Method and Apparatus for Single Step Clocking on Signal Paths Longer Than a Clock Cycle
Patent: 5,055,707 →
Application: 07/568,169 →
Vectorized Lr Parsing of Computer Programs
Patent: 5,193,192 →
Application: 07/571,502 →
Method for Representing Scalar Data Dependences for an Optimizing Compiler
Patent: 5,107,418 →
Application: 07/571,503 →
System for Communicating Among Processors Having Different Speeds
Patent: 5,202,988 →
Application: 07/571,951 →
Computer with Integrated Hierarchical Reprsentation (Ihr) of Program Wherein Ihr File Is Available for Debugging and Optimizing During Target Execution
Patent: 5,175,856 →
Application: 07/572,043 →
Method for Efficient Non-Virtual Main Memory Management
Patent: 5,159,678 →
Application: 07/572,045 →
Dual Contact Beam Assembly for an Ic Test Fixture
Patent: 5,175,496 →
Application: 07/575,935 →
Fault Tolerant Networking Architecture
Patent: 5,206,952 →
Application: 07/582,507 →
High Power, High Density Interconnect Apparatus for Integrated Circuits
Patent: 5,185,502 →
Application: 07/598,103 →
Apparatus for Controlling a Heating Temperature
Patent: 5,272,644 →
Application: 07/612,436 →
Vector Bit-Matrix Multiply Functional Unit
Patent: 5,170,370 →
Application: 07/616,736 →
Methods for Efficient Distribution of Parallel Tasks to Slave Processes in a Multiprocessing System
Patent: 5,257,372 →
Application: 07/630,301 →
Graphical Display of Compiler-Generated Intermediate Database Representation
Patent: 5,187,789 →
Application: 07/640,909 →
Method for Compiling Loops Having Recursive Equations by Detecting and Correcting Recurring Data Points Before Storing the Result to Memory
Patent: 5,247,696 →
Application: 07/642,480 →
System for Distributed Multiprocessor Communication
Patent: 5,434,970 →
Application: 07/655,296 →
Air Jet Impinmgement on Miniature Pin-Fin Heat Sinks for Cooling Electronic Components
Patent: 5,166,775 →
Application: 07/664,940 →
Quick Disconnect System for Circuit Board Modules
Patent: 5,131,859 →
Application: 07/666,356 →
Electromagnetic Shield for Attachment to Computers
Patent: 337,323 →
Application: 07/668,402 →
Apparatus for Sharing Memory in a Multiprocessor System
Patent: 5,142,638 →
Application: 07/682,876 →
Apparatus for Calculating Delay When Executing Vector Tailgating Instructions and Using Delay to Facilitate Simultaneous Reading of Operands from and Writing of Results to Same Vector Register
Patent: 5,349,677 →
Application: 07/683,095 →
Transmission Line with Fluid-Permeable Jacket
Patent: 5,142,100 →
Application: 07/694,467 →
Method and Apparatus for Laser Masking of Lead Bonding
Patent: 5,194,710 →
Application: 07/704,067 →
Method of Manufacturing Interconnect Bumps
Patent: 5,283,948 →
Application: 07/708,447 →
Memory Range Monitoring Apparatus for a Multiprocessor Computer System
Patent: 5,295,260 →
Application: 07/708,461 →
Method and Apparatus for Memory Access in a Matrix Processor Computer
Patent: 6,282,583 →
Application: 07/710,146 →
Metallized Connector Block
Patent: 5,211,567 →
Application: 07/725,007 →
Single Disk Emulation Interface for an Array of Synchronous Spindle Disk Drives
Patent: 5,128,810 →
Application: 07/727,282 →
Computer Mouse
Patent: 373,760 →
Application: 07/733,232 →
Computer Housing
Patent: 341,574 →
Application: 07/733,393 →
Rack and Pinion Retaining and Release Device for Removable Computer Components
Patent: 5,325,263 →
Application: 07/734,142 →
Method of Fabricating Silicon-Based Carriers
Patent: 5,196,377 →
Application: 07/747,523 →
Fiber Optic Channel Extender Interface Method and Apparatus
Patent: 5,390,041 →
Application: 07/788,496 →
A Parallel Vector Processing System for Individual and Braodcast Distribution of Operands and Control Information
Patent: 5,226,171 →
Application: 07/802,643 →
Clock Pulse Measuring and Deskewing System and Process
Patent: 5,329,188 →
Application: 07/803,926 →
Distributing System for Multi-Processor Input and Output Using Channel Adapters
Patent: 5,388,217 →
Application: 07/807,082 →
Optimization of Alternate Loop Exits
Patent: 5,361,354 →
Application: 07/809,390 →
Integrated Circuit Chip Carrier Lid
Patent: 5,258,576 →
Application: 07/816,967 →
Method for Sharing Memory in a Multiprocessor System
Patent: 5,202,970 →
Application: 07/834,867 →
Synchronized Dram Control Apparatus Using Two Different Clock Rates
Patent: 5,179,667 →
Application: 07/840,654 →
Bus Control System for Arbitrating Requests with Predetermined on/Off Time Limitations
Patent: 5,193,193 →
Application: 07/841,908 →
Air Distribution System and Manifold for Cooling Electronic Components
Patent: 5,321,581 →
Application: 07/855,384 →
Multilayer Interconnect System for an Area Array Interconnection Using Solid State Diffusion
Patent: 5,276,955 →
Application: 07/868,531 →
Computer Write-Initiated Special Transferoperation
Patent: 5,261,074 →
Application: 07/869,821 →
Circular Scheduling Method and Apparatus for Executing Computer Programs by Moving Independent Instructions Out of a Loop
Patent: 5,386,562 →
Application: 07/882,427 →
File Alteration Monitor for Computer Operating and File Management System
Patent: 5,287,504 →
Application: 07/882,998 →
Method of Fabricating Metallized Chip Carriers from Wafer-Shaped Substrates
Patent: 5,358,826 →
Application: 07/884,285 →
Solid State Storage Device
Patent: 5,321,697 →
Application: 07/890,026 →
Method for Optimizing Instruction Scheduling for a Processor Having Multiple Functional Resources
Patent: 5,202,975 →
Application: 07/896,895 →
Single Disk Emulation Interface for an Array of Asynchronously Operating Disk Drives
Patent: 5,218,689 →
Application: 07/897,600 →
Fast Interrupt Mechanism for a Interrupting Processors in Parallel in a Multiprocessor System Wherein Processors Are Assigned Process Id Numbers
Patent: 5,193,187 →
Application: 07/898,387 →
Method and Apparatus for a Unified Parallel Processing Architecture
Patent: 5,428,803 →
Application: 07/912,964 →
Method for Clocking Functional Units in One Cycle by Using a Single Clock for Routing Clock Inputs to Initiate Receive Operations Prior to Transmit Operations
Patent: 5,495,596 →
Application: 07/923,086 →
Apparatus and Method for Detecting the Activities of a Plurality of Processors on a Shared Bus
Patent: 5,423,008 →
Application: 07/924,189 →
High Performance Mantissa Divider
Patent: 5,258,944 →
Application: 07/938,715 →
Clock Start Up Stabilization for Computer Systems
Patent: 5,355,397 →
Application: 07/950,628 →
Method for Inserting a Path Instruction During Compliation of Comuter Programs for Processors Having Multiple Functional Units
Patent: 5,307,478 →
Application: 07/969,789 →
Dual Level Scheduling of Processes to Multiple Parallel Regions of a Multi-Threaded Program on a Tightly Coupled Multiprocessor Computer System
Patent: 5,339,415 →
Application: 07/973,598 →
Apparatus for Cooling Daughter Boards
Patent: 5,343,359 →
Application: 07/983,086 →
Direction Order Priority Routing of Packets Between Nodes in a Networked System
Patent: 5,533,198 →
Application: 07/983,979 →
A Computer-Implemented Method and an Apparatus for Converting Data According to a Selected Data Transformation
Patent: 5,694,578 →
Application: 07/993,016 →
Method and Apparatus for User Side Scheduling in a Multiprocessor Operating System Program That Implements Distributive Scheduling of Processes
Patent: 6,195,676 →
Application: 08/003,000 →
Retaining and Release Mechanism for Computer Storage Devices Including a Pawl Latch Assembly
Patent: 5,269,698 →
Application: 08/009,576 →
Synchronized Stereoscopic Display System
Patent: 5,245,319 →
Application: 08/013,165 →
Optical Clock Distribution System
Patent: 5,537,498 →
Application: 08/027,049 →
Error Recovery Method and Apparatus for High Performance Disk Drives
Patent: 5,283,791 →
Application: 08/033,423 →
Method for Use in Designing an Arbitrarily Shaped Object
Patent: 5,453,934 →
Application: 08/038,143 →
Method and Apparatus for Displaying Data Within a Three-Dimensional Information Landscape
Patent: 5,528,735 →
Application: 08/042,801 →
Printed Circuit Board with Cooling Monitoring System
Patent: 5,281,026 →
Application: 08/056,650 →
System Having Integrated Dispatcher for Self Scheduling Processors to Execute Multiple Types of Processes
Patent: 5,452,452 →
Application: 08/072,655 →
Method for Adjusting Clock Skew
Patent: 5,467,040 →
Application: 08/098,204 →
Method of Adjusting for Clock Skew
Patent: 5,414,381 →
Application: 08/098,503 →
A System and Method of Implementing Read Resources to Maintain Cache Coherency in a Multiprocessor Environment Permitting Split Transactions
Patent: 5,504,874 →
Application: 08/128,080 →
System and Method for Piggybacking of Read Responses on a Shared Memory Multiprocessor Bus
Patent: 5,655,102 →
Application: 08/128,081 →
A System and Method for Fair Arbitration on a Multi-Domain Multiprocessor Bus
Patent: 5,509,125 →
Application: 08/128,082 →
System and Method for Generating a Read-Modify-Write Operation
Patent: 5,544,331 →
Application: 08/128,720 →
Multiprocessing System Using Indirect Addressing to Access Respective Local Semaphore Registers Bits for Setting the Bit or Branching If the Bit Is Set
Patent: 5,367,690 →
Application: 08/129,437 →
Method and Apparatus for Locking Shared Memory Locations in Multiprocessing Systems
Patent: 5,535,365 →
Application: 08/141,259 →
Configurable Spare Memory Chips
Patent: 5,392,292 →
Application: 08/149,967 →
System and Method of Addressing Distributed Memory Within a Massively Parallel Processing System
Patent: 5,765,181 →
Application: 08/165,118 →
Barrier Synchronization for Distributed Memory Massively Parallel Processing Systems
Patent: 5,434,995 →
Application: 08/165,265 →
System for Allocating Messages Between Virtual Channels to Avoid Deadlock and to Optimize the Amount of Message Traffic on Each Type of Virtual Channel
Patent: 5,583,990 →
Application: 08/165,266 →
Method for the Dynamic Allocation of Array Sizes in a Multiprocessor System
Patent: 5,586,325 →
Application: 08/165,379 →
Recursive Address Centrifuge for Distributed Memory Massively Parallel Processing Systems
Patent: 5,696,922 →
Application: 08/165,388 →
Repetitive Signal Detector for Preventing Thermal Runaway
Patent: 5,418,481 →
Application: 08/165,747 →
Virtual to Logical to Physical Address Translation for Distributed Memory Massively Parallel Processing Systems
Patent: 5,784,706 →
Application: 08/165,814 →
Method of Managing Distributed Memory Within a Massively Parallel Processing System
Patent: 5,566,321 →
Application: 08/166,293 →
Messaging Facility with Hardware Tail Pointer and Software Implemented Head Pointer Message Queue for Distributed Memory Massively Parallel Processing System
Patent: 5,581,705 →
Application: 08/166,443 →
Method for the Dynamic Allocation of Page Sizes in Virtual Memory
Patent: 5,802,341 →
Application: 08/166,451 →
Bracket for a Cpu Daughter Card
Patent: 5,465,934 →
Application: 08/168,165 →
Disk Drive Bracket
Patent: 5,564,804 →
Application: 08/168,166 →
Method and Apparatus for a Multiprocessor Resource Lockout Instruction
Patent: 5,499,356 →
Application: 08/173,923 →
System and Method of Generating Object Code Using Aggregate Instruction Movement
Patent: 5,557,761 →
Application: 08/186,248 →
Loop Scheduler
Patent: 5,491,823 →
Application: 08/186,268 →
Real Time I/O Operation in a Vector Processing Computer System by Running Designated Processors in Privileged Mode and Bypass the Operating System
Patent: 5,390,300 →
Application: 08/200,921 →
Arrangement for Modifying Electrical Printed Circuit Boards
Patent: 5,834,705 →
Application: 08/205,990 →
Vector Shift Functional Unit for Successively Shifting Operands Stored in a Vector Register by Corresponding Shift Counts Stored in Another Vector Register
Patent: 5,481,746 →
Application: 08/218,997 →
Optical Clock Distribution Method and Apparatus
Patent: 5,442,475 →
Application: 08/231,996 →
Apparatus and Method for Testing of New Operating Systems Through Privileged Instruction Trapping
Patent: 5,371,879 →
Application: 08/233,222 →
Method and Apparatus for Separate Mark and Wait Instructions for Processors Having Multiple Memory Ports
Patent: 5,381,536 →
Application: 08/249,084 →
Interleaved Memory Access System Having Variable-Sized Segments Logical Address Spaces and Means for Dividing/Mapping Physical Address into Higher and Lower Order Addresses
Patent: 5,561,784 →
Application: 08/268,660 →
Three Dimensional Model with Three Dimensional Pointers and Multimedia Functions Linked to the Pointers
Patent: 5,526,478 →
Application: 08/269,444 →
Responding to Service Requests Using Minimal System-Side Context in a Multiprocessor Environment
Patent: 5,390,329 →
Application: 08/277,776 →
System and Method for Conditionally Compiling a Software Compilation Unit
Patent: 5,692,196 →
Application: 08/294,823 →
System and Method for Enabling, Without Recompilation, Modification of Class Definitions and Implementations in an Object-Oriented Computer Program
Patent: 5,613,120 →
Application: 08/325,155 →
Extendible Clock Mechanism
Patent: 5,625,831 →
Application: 08/331,730 →
Stream Buffers for High-Performance Computer Memory Systems
Patent: 5,761,706 →
Application: 08/333,133 →
Apparatus and Method for Testing Using Clocked Test Access Port Controller for Level Sensitive Scan Designs
Patent: 6,173,428 →
Application: 08/340,238 →
Outer Loop Vectorization
Patent: 5,802,375 →
Application: 08/344,236 →
Associative Scalar Data Cache with Write-Through Capabilities for a Vector Processor
Patent: 5,717,895 →
Application: 08/348,056 →
A Central Processing Unit for Processing a Plurality of Threads Using Dedicated General Purpose Registers and Masque Register for Providing Access to the Registers
Patent: 5,524,250 →
Application: 08/363,599 →
Method and Apparatus for Accessing Global Registers in a Multiprocessor System
Patent: 5,524,255 →
Application: 08/379,123 →
Method and Apparatus for Chaining Vector Instructions
Patent: 5,640,524 →
Application: 08/395,320 →
Boundary Scan Testing Using Clocked Signal
Patent: 5,487,074 →
Application: 08/406,571 →
Communication Protocol for Transferring Information Across a #S Serial Communication Link
Patent: 5,592,487 →
Application: 08/407,808 →
Adaptive Routing Mechanism for Torus Interconnection Network
Patent: 5,701,416 →
Application: 08/421,566 →
System for Randomly Modifying Virtual Channel Allocation and Accepting the Random Modification Based on the Cost Function
Patent: 5,659,796 →
Application: 08/422,072 →
Efficient Ultra Low Drop Out Power Regulator
Patent: 5,736,843 →
Application: 08/431,704 →
Hierarchical Fat Hypercube Architecture for Parallel Processing Systems
Patent: 5,669,008 →
Application: 08/435,451 →
Programmable, Distributed Network Routing
Patent: 5,721,819 →
Application: 08/435,452 →
A System and Method for the Synchronous Transmission of Data in a Communication Network Utilizing a Source Clock Signal to Latch Serial Data into First Registers and a Handshake Signal to Latch Parallel Data into Second Registers
Patent: 5,768,529 →
Application: 08/435,453 →
Distributed Global Clock System
Patent: 5,822,381 →
Application: 08/435,455 →
System and Method for Network Exploration and Access
Patent: 5,682,479 →
Application: 08/435,456 →
System and Method for Maintaining Coherency of Virtual-to-Physical Memory Tranlations in a Multiprocessor Computer
Patent: 5,787,476 →
Application: 08/435,459 →
Directory-Based Coherence Protocol Allowing Efficient Dropping of Clean-Exclusive Data
Patent: 5,680,576 →
Application: 08/435,460 →
System and Method for Multiprocessor Partitioning to Support High Availability
Patent: 5,991,895 →
Application: 08/435,462 →
Cache Coherency Using Flexible Directory Bit Vectors
Patent: 5,634,110 →
Application: 08/435,463 →
Barrier and Eureka Synchronization Architecture for Multiprocessors
Patent: 5,721,921 →
Application: 08/450,251 →
System and Method for Optimizing a Source Code Representation as a Function of Resource Utilization
Patent: 5,734,908 →
Application: 08/455,238 →
A Computer-Implemented Method and an Apparatus for Inputting Data Structure Characteristics
Patent: 5,652,874 →
Application: 08/478,802 →
Vector Processor Having Functional Unit Paths of Differing Pipeline Lengths
Patent: 5,598,547 →
Application: 08/478,815 →
Data Processing System for Processing One and Two Parcel Instructions
Patent: 5,717,881 →
Application: 08/481,060 →
Method of Processing Conditional Branch Instructions in Scalar/Vector Processor
Patent: 5,706,490 →
Application: 08/484,103 →
Method of Processing a Sequence of Conditional Vector If Statements
Patent: 5,623,650 →
Application: 08/484,124 →
Partitioned Addressing Apparatus for Vector/Scalar Registers
Patent: 5,745,721 →
Application: 08/485,017 →
Vector/Scalar Processor with Simultaneous Processing and Instruction Cache Filling
Patent: 5,659,706 →
Application: 08/486,612 →
Vector Processor Having Registers for Control by Vector Registers
Patent: 5,544,337 →
Application: 08/487,952 →
Heatsink and Method of Forming a Heatsink
Patent: 5,829,512 →
Application: 08/520,408 →
Cross-Module Optimization for Dynamically-Shared Programs and Libraries
Patent: 5,923,882 →
Application: 08/521,027 →
Vector Word Shift by Vo Shift Count in Vector Supercomputer Processor
Patent: 5,848,286 →
Application: 08/521,566 →
Four-Dimensional Graphical User Interface
Patent: 5,678,015 →
Application: 08/522,953 →
System and Merthod for Uncached Store Buffering in a Microprocessor
Patent: 5,963,981 →
Application: 08/539,524 →
Configuring of Networked System to Permit Replacement of Failed Nodes and Selection of Alternate Paths
Patent: 5,689,646 →
Application: 08/541,803 →
Acknowledge Triggered Forwarding of External Block Data Responses in a Microprocessor
Patent: 5,832,306 →
Application: 08/544,537 →
Virtual Maintenance Network in Multiprocessing System Having a Non- Flow Controlled Virtual Maintenance Channel
Patent: 6,055,618 →
Application: 08/550,992 →
High Performance Spiral Heat Sink
Patent: 5,661,638 →
Application: 08/552,801 →
System and Method for Allowing a Performer to Control and Interact with an on-Stage Display Device
Patent: 5,790,124 →
Application: 08/561,183 →
Readily Removable Heat Sink Assembly
Patent: 5,662,163 →
Application: 08/564,404 →
Scan Chain for Shiting the State of a Processor into Memory at a Specified Point During System Operation for Testing Purposes
Patent: 5,671,235 →
Application: 08/567,082 →
Operating System Having a Mechanism for Handling a Group of Related Processes Redising on Separate Machines
Patent: 6,279,028 →
Application: 08/569,463 →
System and Method for Coordinating Communication Between Layers of a Layered Communication System
Patent: 5,784,567 →
Application: 08/571,366 →
A System and Method of Implementing Read Resources to Maintain Cache Coherency in a Multiprocessor Environment Permitting Split Transactions
Patent: 5,664,151 →
Application: 08/578,997 →
System and Method for an Iconic Drag and Drop Interface for Electronic File Transfer
Patent: 5,801,700 →
Application: 08/588,844 →
Processor-Inclusive Memory Module
Patent: 5,710,733 →
Application: 08/589,532 →
Method for Selecting a Three-Dimensional Object from a Graphical User Interface
Patent: 5,694,532 →
Application: 08/590,561 →
Collaborative Work Environment Supporting Three-Dimensional Objects and Multiple, Remote Participants
Patent: 5,821,925 →
Application: 08/590,562 →
System and Method to Reduce Phase Offset and Phase Jitter in Phase-Locked and Delay-Locked Loops Using Self-Biased Circuits
Patent: 5,727,037 →
Application: 08/592,736 →
Single Connector Attachment Drive Sled Assembly Having Light Pipe Coupled to a Rail
Patent: 5,654,873 →
Application: 08/592,890 →
Method for Seeding a Pseudo-Random Number Generator with a Cryptographic Hash of a Digitization of a Chaotic System
Patent: 5,732,138 →
Application: 08/592,891 →
Transparent Relocation of Real Memory Addresses in the Main Memory of a Data Processor
Patent: 5,765,198 →
Application: 08/595,528 →
Daughter Card Assembly
Patent: 5,761,043 →
Application: 08/604,839 →
Method and Apparatus for Cooling Daughter Card Modules
Patent: 5,801,924 →
Application: 08/604,888 →
Cooling Cap Method and Apparatus for Tab Packaged Integrated Circuits
Patent: 5,805,418 →
Application: 08/604,918 →
Cooling Approach for High Power Integrated Circuits Mounted on Printed Circuit Boards
Patent: 5,768,104 →
Application: 08/605,355 →
Bga Land Pattern
Patent: 6,091,155 →
Application: 08/606,291 →
System and Method to Reduce Jitter in Digital Delay-Locked Loops
Patent: 5,790,612 →
Application: 08/609,068 →
Procedure and System for Placement Optimization of Cells Within Circuit Blocks by Optimizing Placement of Input/Output Ports Within an Integrated Circuit Design
Patent: 5,757,658 →
Application: 08/611,785 →
Massively Parallel Processing System Using Two Data Paths: One Connecting Router Circuit to the Interconnect Network and the Other Connecting Router Circuit to I/O Controller
Patent: 5,864,738 →
Application: 08/614,859 →
System and Method for Fault-Tolerant Transmission of Data Within a Dual Ring Network
Patent: 6,233,704 →
Application: 08/614,860 →
Using External Registers to Extend Memory Reference Capabilities of a Microprocessor
Patent: 5,835,925 →
Application: 08/615,671 →
Messaging in Distributed Memory Multiprocessing System Having Shell Circuitry for Atomic Control of Message Storage Queue's Tail Pointer Structure in Local Memory
Patent: 5,841,973 →
Application: 08/615,694 →
Adaptive Congestion Control Mechanism for Modular Computer Networks
Patent: 5,748,900 →
Application: 08/615,700 →
Mechanism for Non-Linear Browsing of Diverse Information Sources
Patent: 5,835,092 →
Application: 08/629,967 →
System and Method to Efficiently Represent Aliases and Indirect Memory Operations in Static Single Assignment Form During Compilation
Patent: 5,768,596 →
Application: 08/636,605 →
Multi-Configurable Push-Pull/Open-Drain Driver Circuit
Patent: 5,811,997 →
Application: 08/638,186 →
System and Method for Processing Graphic Language Characters
Patent: 5,802,482 →
Application: 08/638,217 →
Heat Sink with Integral Attachment Mechanism
Patent: 5,735,340 →
Application: 08/649,769 →
Raid-5 Parity Generation and Data Reconstruction
Patent: 5,805,788 →
Application: 08/650,336 →
Method and Apparatus for Adjusting the Power Supply Voltage Provided to a Microprocessor
Patent: 5,694,028 →
Application: 08/650,337 →
A System for Arbitrating Packetized Data from the Network to the Peripheral Resources and Prioritizing the Dispatching of Packets Onto the Network
Patent: 5,761,534 →
Application: 08/650,630 →
A Raid System Using I/O Buffer Segment to Temporary Store Striped and Parity Data and Connecting All Disk Drives via a Single Time Multiplexed Network
Patent: 5,862,313 →
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Interprocedural Analysis User Interface
Patent: 5,778,212 →
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System and Method for Constant Propagation Cloning for Unknown Edges in Ipa
Patent: 5,812,855 →
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Networked Multiprocessor System with Global Distributed Memory and Block Transfer Engine
Patent: 5,797,035 →
Application: 08/661,908 →
Multiprocessor Computer System with Interleaved Processing Element Nodes
Patent: 5,737,628 →
Application: 08/662,868 →
Method and Apparatus for Removing Power-of-Two Restrictions on Distributed Addressing
Patent: 5,900,023 →
Application: 08/673,436 →
Apparatus and Method for Determining the Speed of a Semiconductor Chip
Patent: 5,818,250 →
Application: 08/675,849 →
Compiler Having Automatic Common Blocks of Memory Splitting
Patent: 5,848,275 →
Application: 08/688,020 →
Apparatus and Method for Dynamic Central Processing Unit Clock Adjustment
Patent: 5,774,704 →
Application: 08/688,501 →
Bulkhead Gasket Assembly
Patent: 5,770,822 →
Application: 08/697,073 →
Density Dependent Vector Mask Operation Control Apparatus and Method
Patent: 5,940,625 →
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Method to Pipeline Write Misses in Shared Cache Multiprocessor Systems
Patent: 5,875,468 →
Application: 08/708,298 →
Method and System for an Efficient User Mode Cache Manipulation Using a Simulated Instruction
Patent: 6,049,866 →
Application: 08/709,005 →
Method and Apparatus for Address Space Translation Using a Tlb
Patent: 5,815,686 →
Application: 08/712,889 →
Compression Connector
Patent: 5,730,605 →
Application: 08/713,283 →
Compression and Decompression Scheme Performed on Shared Workstation Memory by Media Coprocessor
Patent: 5,768,445 →
Application: 08/713,599 →
Circuit to Separate and Combine Color Space Component Data of a Video Image
Patent: 5,835,729 →
Application: 08/713,600 →
Disk Drive Loading Mechanism
Patent: 5,790,373 →
Application: 08/713,601 →
Direct Memory Access Apparatus for Transferring a Block of Data Having Discontinuous Addresses Using an Address Calculating Circuit
Patent: 6,108,722 →
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Resilient Panel for Housing a Machine
Patent: 5,897,180 →
Application: 08/716,928 →
Instruction Methods for Performing Data Formatting While Moving Data Between Memory and a Vector Register File
Patent: 5,812,147 →
Application: 08/716,972 →
Guaranteed Bandwidth Allocation Method in a Computer System for Input/Output Data Transfers
Patent: 5,784,569 →
Application: 08/717,581 →
Synchronization Infrastructure for Use in a Computer System
Patent: 5,764,965 →
Application: 08/717,860 →
Cable Management System for a Computer
Patent: 5,957,556 →
Application: 08/717,988 →
Raid System with Fibre Channel Arbitrated Loop
Patent: 5,812,754 →
Application: 08/718,743 →
Adaptive Frequency Synthesizer with Synchronization
Patent: 6,067,411 →
Application: 08/718,765 →
Interactive Selection of 3-D on-Screen Objects Using Active Selection Entities Provided to the User
Patent: 5,982,382 →
Application: 08/747,939 →
High Memory Capacity Dimm with Data and State Memory
Patent: 5,790,447 →
Application: 08/747,975 →
Dimm Pair with Data Memory and State Memory
Patent: 5,686,730 →
Application: 08/747,976 →
Low-Latency Real-Time Dispatching in General Purpose Multiprocessor Systems
Patent: 5,928,322 →
Application: 08/752,925 →
Apparatus and Method for Page Migration in a Non-Uniform Memory Access (Numa) System
Patent: 5,727,150 →
Application: 08/766,363 →
Programmable Packer and Unpacker with Ditherer
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High Bandwidth Pci to Packet Switched Router Bridge Having Minimized Memory Latency
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Apparatus and Method for Compiler Identification of Address Data
Patent: 6,059,839 →
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Packetized Data Transmissions in a Switched Router Architecture
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Circuit for Filtering a Power Supply for Noise Sensitive Devices
Patent: 5,825,238 →
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Processor-Inclusive Memory Module
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Power Switch Plunger Mechanism
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Light Bar and Reflector Assembly
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Method and System for Simultaneous High Bandwidth Input Output
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Loading and Placement Device for Connecting Circuit Boards
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Resumption of Preempted Non-Privileged Threads with No Kernel Intervention
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System for Communications Where First Priority Data Transfer Is Not Disturbed by Second Priority Data Transfer and Where Allocated Bandwidth Is Removed When Process Terminates Abnormally
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System and Method for Automatically Creating a Desktop Icon for Access to a Remote Resource
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System and Method for Scheduling an Event Subject to the Availability of Requested Participants
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Method for Selecting Optimal Parameters for Compiling Source Code
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Rotary Latch Assembly for a Computer Housing
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System and Method for Independently Configuring International Location and Language
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Method System and Computer Program Product for Visualizing Data Using Partial Hierarchies
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Method, System and Computer Program Product for Navigating Through Partial Hierarchies
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Network Request Distribution Based on Static Rules and Dynamic Performance Data
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Embedding a Digital Signature in a Video Sequence
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System, Method, and Computer Program Product for Partial Redundancy Elimination Based on Static Single Assignment Form During Compilation
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Electromagnetic Interference Shielding Enclosure and Heat Sink with Compression Coupling Mechanism
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An Apparatus for Generating Differential Noise Between Power and Ground Planes
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Method and System for Deskewing Parallel Bus Channels
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Recursive Address Centrifuge for Distributed Memory Massively Parallel Processing Systems
Patent: 6,119,198 →
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Method and Apparatus for Extraction of Program Region
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System and Method for Input/Output Flow Control in a Multiprocessor Computer System
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Processor-Inclusive Memory Module
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Method, System and Computer Program Product for Profiling Thread Virtual Memory Accesses
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Integral Actuator for a Printed Circuit Board
Patent: 5,967,825 →
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System and Method for Maintaining Translation Look- Aside Buffer (Tlb)Consistency
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Precise Detection of Errors Using Hardware Watchpoint Mechanism
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System Method and Computer Program Product for Organizing Page Caches
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Method, System, and Computer Program Product for Page Replication in a Non-Uniform Memory Access System
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Stop Align Lateral Module to Module Interconnect
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System and Method for Distributed Multiprocessor Communications
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Adaptive Bandwidth Sharing
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Method, System, and Computer Program Product for Allocating Physical Memory in a Distributed Shared Memory Network
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Method, System and Computer Program Product for Managing Memory in a Non-Uniform Memory Access System
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Reverse Mapping Page Frame Data Structures to Page Table Entries.
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System, Method and Computer Program Product for Inter-Cell Page Sharing in a Distributed Shared Memory System
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Demateable, Compliant, Area Array Interconnect
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Adaptive Congestion Control Mechanism for Modular Computer Networks
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Method, System and Computer Program Product for Virtual Memory Support for Managing Translation Look Aside Buffers with Multiple Page Size Support
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Method, System and Computer Program Product for Dynamically Allocating Large Memory Pages of Different Sizes
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System Method and Computer Program Product for Dynamically Sizing Hash Tables
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Sliding Door Assembly for a Computer Housing
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System and Method for Performing High-Precision Multi-Channel Blending Using Multiple Blending Passes
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Porous Metal Heat Sink
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Data Processing Synchronization with Automatic Queuing
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Router Table Lookup Mechanism
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Hybrid Hypercube/Torus Architecture
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Virtual Channel Assignment in Large Torus Systems
Patent: 6,101,181 →
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Serialized Race-Free Virtual Barrier Network
Patent: 6,085,303 →
Application: 08/972,010 →
Improved Hot- Plug Power Supply for High- Availability Computer Systems
Patent: 6,044,424 →
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Interleaving Memory in Distributed Vector Architecture Multiprocessor System
Patent: 5,913,069 →
Application: 08/987,948 →
Distributed Vector Architecture
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Application: 08/988,524 →
Message Buffering for a Computer-Based Network
Patent: 6,256,677 →
Application: 08/991,233 →
Modular Card Cage
Patent: 6,171,120 →
Application: 09/005,219 →
Method of Handling Arbitrary Size Message Queues in Which a Message Is Written into an Aligned Block of External Registers Within a Plurality of External Registers
Patent: 6,029,212 →
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The Fabrication of Test Logic for Level Sensitive Scan on a Circuit
Patent: 6,092,226 →
Application: 09/021,651 →
Diamond-Based Transformers and Power Convertors
Patent: 6,181,231 →
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System and for Stacking of Integrated Circuit Packages
Patent: 6,172,874 →
Application: 09/055,677 →
Large Area, Multi-Device Heat Pipe for Stacked Mcm-Based Systems
Patent: 6,055,157 →
Application: 09/056,037 →
Quantum Acceleration of Conventional Non-Quantum Computers
Patent: 6,081,882 →
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Memory System with Multiple Addressing and Control Busses
Patent: 5,870,325 →
Application: 09/060,451 →
Method and System for Decoding Data Encoded in a Variable Length Code Word
Patent: 6,219,457 →
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System and Method for Coding Colors and Storing Compensation Factors Used in Color Space Conversion
Patent: 5,995,655 →
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Method and System for Efficient Context Switching in a Computer Graphics System
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Method, System, and Computer Program Product for Performing Register Promotion via Load and Store Placement Optimization Within an Optimizing Compiler
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Method, System, and Computer Program Product for Extending Sparse Partial Redundancy Elimination to Support Speculative Code Motion Within an Optimizing Compiler
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Hashed Direct-Mapped Texture Cache
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Eigen-Mode Encoding of Signals in a Data Group
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System and Method for Maintaining Coherency of Virtual-to-Physical Memory Translations in a Multiprocessor Computer
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High Memory Capacity Dimm with Data and State Memory
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Cooling Cap Method and Apparatus for Tab Packaged Integrated Circuit
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Media Coprocessor with Graphics Video and Audio Tasks Partitioned by Time Division Multiplexing
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Vector Shift Functional Unit for Successively Shifting Operands Stored in a Vector Register by Corresponding Shift Counts Stored in Another Vector Register
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Method and System for Performing Floating Point Operations in Unnmormalized Format Using a Floating Point Accumulator
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Automatic Frame Accumulator
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System and Method for Fast Barrier Synchronization
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Collaborative Work Environment Supporting Three-Dimensional Objects and Multiple, Remote Participants
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Array Address and Loop Alignment Calculations
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Advanced Boot Sequence for an X86 Computer System That Maintains Expansion Card Device Compatibility
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Memory System with Multiple Addressing and Control Busses
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High Performance Gas Cooling System and Method
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Memory System with Switching for Data Isolation
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Method for Efficient Translation of Memory Addresses in Computer Systems
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Design for Circuit Board Orthogonal Installation and Removal
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Door Assembly for a Computer
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Memory System with Switching for Data Isolation
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Printed Circuit Board Carrier Insertion/Extraction Assembly
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Configurable Synchronizer for Double Data Rate Synchronous Dynamic Random Access Memory
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System and Method to Provide Power to a Sea of Gates Standard Cell Block from an Overhead Bump Grid
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Cable Dock Fixture with Emi Shielding
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Metered force single point heatsink attach mechanism
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Top Front and Side Portions of a Combined Computer Housing and Support Stands
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Top, Sides and Front Portions of a Computer Housing
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Pushbutton Remote Control
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Housing for Deskside Computer
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Compact Computer Housing
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Housing for a Computer
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Compact Computer Housing
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Display Assembly
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Computer Housing
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Computer Housing
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Color Calibration Device for a Display
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Bezel for a Computer
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Radial Computer System
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Drive sled handle
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Drive sled cover
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Front panel media door
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Related Assignments (22)
Other recorded transfers of the patents in this record — the chain of ownership.
Security Interest Dec 29, 2003
From: SILICON GRAPHICS, INC.
To: U.S. BANK NATIONAL ASSOCIATION, AS TRUSTEE
Reel/Frame 014805/0855 →
Security Interest Oct 24, 2006
From: SILICON GRAPHICS, INC.
To: GENERAL ELECTRIC CAPITAL CORPORATION
Reel/Frame 018545/0777 →
Assignment of Assignor's Interest Oct 18, 2007
From: GENERAL ELECTRIC CAPITAL CORPORATION
To: MORGAN STANLEY & CO., INCORPORATED
Reel/Frame 019995/0895 →
Assignment of Assignor's Interest Feb 16, 2012
From: SILICON GRAPHICS, INC. ET AL.; SGI INTERNATIONAL, INC.
To: SILICON GRAPHICS INTERNATIONAL, CORP.
Reel/Frame 027727/0020 →
Assignment of Assignor's Interest Feb 16, 2012
From: SILICON GRAPHICS, INC. ET AL.; SGI INTERNATIONAL, INC.
To: SILICON GRAPHICS INTERNATIONAL, CORP.
Reel/Frame 027717/0868 →
Assignment of Assignor's Interest Feb 16, 2012
From: SILICON GRAPHICS, INC. ET AL.; SGI INTERNATIONAL, INC.
To: SILICON GRAPHICS INTERNATIONAL, CORP.
Reel/Frame 027727/0086 →
Change of Name Apr 18, 2012
From: SILICON GRAPHICS, INC.
To: GRAPHICS PROPERTIES HOLDINGS, INC.
Reel/Frame 028066/0415 →
Assignment of Assignor's Interest Jan 4, 2013
From: GRAPHICS PROPERTIES HOLDINGS, INC.
To: RPX CORPORATION
Reel/Frame 029564/0799 →
Assignment of Assignor's Interest Apr 18, 2014
From: SILICON GRAPHICS, INC.
To: SILICON GRAPHICS INTERNATIONAL, INC.
Reel/Frame 032714/0032 →
Change of Name Apr 18, 2014
From: SILICON GRAPHICS INTERNATIONAL, INC.
To: SGI INTERNATIONAL, INC.
Reel/Frame 032714/0230 →
Merger Apr 18, 2014
From: SGI INTERNATIONAL, INC.
To: SILICON GRAPHICS INTERNATIONAL CORP.
Reel/Frame 032714/0427 →
Merger Jul 26, 2016
From: CRAY RESEARCH, INC.
To: CRAY RESEARCH, L.L.C.
Reel/Frame 039474/0796 →
Order...Authorizing the Sale of All or Substantially All of the Assets of the Debtors Free and Clear of All Liens, Encumbrances, and Interests. Jul 26, 2016
From: FOOTHILL CAPITAL CORPORATION
To: SILICON GRAPHICS, INC.
Reel/Frame 039474/0606 →
Order...Authorizing the Sale of All or Substantially All of the Assets of the Debtors Free and Clear of All Liens, Encumbrances, and Interests. Jul 26, 2016
From: MORGAN STANLEY & CO., INCORPORATED
To: SILICON GRAPHICS, INC.
Reel/Frame 039482/0015 →
Order. . .Authorizing the Sale of All or Substantially All of the Assets of the Debtors Free and Clear of All Liens, Claims, Encumbrances, and Interests Jul 27, 2016
From: U.S. BANK NATIONAL ASSOCIATION, AS TRUSTEE
To: SILICON GRAPHICS, INC
Reel/Frame 039484/0869 →
Merger Oct 13, 2016
From: SGI INTERNATIONAL, INC.
To: SILICON GRAPHICS INTERNATIONAL CORP.
Reel/Frame 040010/0219 →
Change of Name Oct 13, 2016
From: SILICON GRAPHICS INTERNATIONAL, INC.
To: SGI INTERNATIONAL, INC.
Reel/Frame 040350/0810 →
Assignment of Assignor's Interest Oct 13, 2016
From: SILICON GRAPHICS, INC.
To: SILICON GRAPHICS INTERNATIONAL, INC.
Reel/Frame 040350/0739 →
Merger Oct 21, 2016
From: SGI INTERNATIONAL, INC.
To: SILICON GRAPHICS INTERNATIONAL CORP.
Reel/Frame 040459/0518 →
Change of Name Oct 21, 2016
From: SILICON GRAPHICS INTERNATIONAL, INC.
To: SGI INTERNATIONAL, INC.
Reel/Frame 040459/0157 →
Assignment of Assignor's Interest Oct 21, 2016
From: SILICON GRAPHICS, INC
To: SILICON GRAPHICS INTERNATIONAL, INC.
Reel/Frame 040459/0026 →
Assignment of Assignor's Interest Oct 4, 2017
From: SILICON GRAPHICS INTERNATIONAL CORP.
To: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP
Reel/Frame 044128/0149 →