Patent Assignment
Reel/Frame 015334/0772
Assignment of Assignor's Interest
Recorded: 2004-05-24
Received: 2004-05-26
Pages: 18
Assignor
MOSEL VITELIC, INC.
Executed: 2004-04-27
Assignee
PROMOS TECHNOLOGIES INC.
3F, NO.19, LI-HSIN ROAD, SCIENCE-BASED INDUSTRIAL PARK, HSIN-CHU CITY, TWX, TAIWAN
Covered Properties
(36)
Isolation of Spore-Like Cells from Tissues Exposed to Extreme Conditions
Application:
10/792,302 →
Trench Capacitor with Expanded Area and Method of Making the Same
Application:
10/317,912 →
Integrated Data Input Sorting and Timing Circuit for Double Data Rate (Ddr) Dynamic Random Access Memory (Dram) Devices
Application:
10/287,210 →
Method and Device for Providing Double Cell Density in Sdram and in Ddr Sdram
Application:
10/272,312 →
Nonvolatile Memories with Floating Gate Spacers, and Methods of Fabrication
Application:
10/199,157 →
Fabrication of Dielectric in Trenches Formed in a Semiconductor Substrate for a Nonvolatile Memory
Application:
10/174,442 →
Polishing of Conductive Layers in Fabrication of Integrated Circuits
Application:
10/174,431 →
Fabricating a Dmos Transistor
Application:
10/160,299 →
Electrically Erasable Programmable Read-Only Memory and Method of Erasing Select Memory Cells
Application:
10/155,953 →
Sidewall Protection in Fabrication of Integrated Circuits
Application:
10/146,979 →
Method for Assembling Motor Assembly to Support Wafer
Application:
10/106,676 →
System for Sensing Position of Spin Dryer Cover
Application:
10/087,096 →
Method for Measuring the Depth of Well
Application:
10/074,852 →
Auxiliary Tool for Assembling a Scrubber
Application:
10/074,953 →
System and Method for Eliminating Pulse Width Variations in Digital Delay Lines
Application:
10/007,875 →
Forming Conductive Layers on Insulators by Physical Vapor Deposition
Application:
09/976,392 →
Nonvolatile Memory Structures and Fabrication Methods
Application:
09/974,455 →
Nonvolatile Memory Structures and Access Methods
Application:
09/972,388 →
Method of Power Ic Inspection
Application:
09/969,601 →
Integrated Data Input Sorting and Timing Circuit for Double Data Rate (Ddr) Dynamic Random Access Memory (Dram) Devices
Application:
09/955,234 →
Nonvolatile Memory Structures and Fabrication Methods
Application:
09/952,817 →
Method for Forming a Dielectric Layer in a Semiconductor Device by Using Etch Stop Layers
Application:
09/929,098 →
Method for Manufacturing a Non-Volatile Memory Device from a Single Polysilicon Layer
Application:
09/915,928 →
Apparatus and Method for Determining Various Processes of Wafer Fabrication in a Semiconductor Device Manufacturing Technology
Application:
09/894,753 →
Mos Transistors Having Dual Gates and Self-Aligned Interconnect Contact Windows
Application:
09/896,205 →
Few-Particle-Induced Low-Pressure Teos Process
Application:
09/888,398 →
Method of Prevent an Etcher from Being Eroded
Application:
09/888,397 →
Nonvolatile Memories with Floating Gate Spacers, and Methods of Fabrication
Application:
09/881,288 →
Formation of Tungsten-Based Interconnect Using Thin Physically Vapor Deposited Titanium Nitride Layer
Application:
09/881,607 →
Coupling for a Reflectivity-Measuring Device
Application:
09/864,372 →
Teaching Tool for a Robot Arm for Wafer Reaction Ovens
Application:
09/863,329 →
Method for protecting stepper alignment marks
Application:
09/854,952 →
Dummy Structures That Protect Circuit Elements During Polishing
Application:
09/846,123 →
New Poly Spacer Split Gate Cell with Extremely Small Cell Size
Application:
09/822,563 →
Fabrication of a T-Shaped Capacitor
Application:
09/816,946 →
System and Method for High Speed Integrated Circuit Device Testing Utilizing a Lower Speed Test Environment
Application:
09/815,146 →