Multi-rate serializer/deserializer circuit with broad operating frequency range
View Patent ↗A serializer and deserializer utilize upsampling and downsampling to operate over a broad range of frequencies. The serializer includes a bit repeater and a high-speed serializer. The bit repeater receives data to be serialized, upsamples the received data, and supplies the upsampled data to the high-speed serializer. The deserializer includes a high-speed deserializer and a downsampler. The high-speed deserializer supplies parallelized data to the downsampler. The downsampler decimates the parallelized data and supplies the decimated data to an output of the deserializer.
1. An integrated circuit comprising:
high-speed serializer circuitry configured to operate at a data rate at least as fast as the fastest of a plurality of different selectable data rates;
bit repeater circuitry configured to receive repeater input words, produce N copies of each bit of the repeater input words in consecutive bit positions of repeater output words, where the consecutive bit positions wrap over multiple repeater output words, and supply the repeater output words to the high-speed serializer circuitry at the operating data rate of the high-speed serializer circuitry, wherein N is an integer greater than 1;
high-speed deserializer circuitry configured to operate at the data rate at least as fast as the fastest of the plurality of different selectable data rates; and
downsampler circuitry configured to receive downsampler input words from the high-speed deserializer circuitry at the operating data rate of the high-speed deserializer circuitry, produce parallel received signals, where the parallel received signals are selected from a logical concatenation of N downsampler input words, and supply the parallel received signals at a selected one of the plurality of different selectable data rates.
2. The integrated circuit of claim 1 , wherein N is proportional to the ratio of the operating data rate of the high-speed serializer circuitry and the selected one of the plurality of different selectable data rates.
3. The integrated circuit of claim 1 , wherein the parallel received signals are selected from every N-th bit of the logical concatenation of the N downsampler input words, where N is the ratio of the operating data rate of the high-speed deserializer circuitry and the selected one of the plurality of different selectable data rates.
4. The integrated circuit of claim 1 , further comprising receive processing circuitry configured to receive the parallel received signals from the downsampler circuitry and supply processed signals at the selected one of the plurality of different selectable data rates.
5. The integrated circuit of claim 1 , further comprising transmit processing circuitry configured to receive input data and supply the repeater input words to the bit repeater circuitry at the selected one of the plurality of different selectable data rates.
6. The integrated circuit of claim 1 , wherein the repeater input words received by the bit repeater circuitry comprises parallel data signals.
7. The integrated circuit of claim 1 , wherein the repeater output words supplied by the bit repeater circuitry to the high-speed serializer circuitry comprises parallel data signals.
8. The integrated circuit of claim 7 , wherein the high-speed serializer circuitry is further configured to produce a serial output signal utilizing the repeater output words supplied by the bit repeater circuitry.
9. The integrated circuit of claim 1 , wherein the downsampler input words supplied by the high-speed deserializer circuitry to the downsampler circuitry comprises parallel data signals.
10. The integrated circuit of claim 9 , wherein the high-speed deserializer circuitry is further configured to produce the downsampler input words supplied to the downsampler circuitry utilizing a received serial input signal.
11. The integrated circuit of claim 1 , wherein the parallel received signals supplied by the downsampler circuitry comprises parallel data signals.
12. The integrated circuit of claim 1 , wherein the number of copies, N, of each bit of the repeater input words is indicated by a rate control signal.
13. The integrated circuit of claim 1 , further comprises a FIFO to rate buffer the repeater input words.
14. The integrated circuit of claim 13 , further comprises an encoder to receive the rate buffered repeater input words and encode the rate buffered repeater input words using 8B10B code.
15. The integrated circuit of claim 1 , further comprises an aligner to receive the parallel received signals and supply aligned signals.
16. The integrated circuit of claim 15 , further comprises a decoder to decode the aligned signals using 8B10B code.