IP Library Granted Patent US 10,283,444
Granted Patent B2
US 10,283,444 · App. 15/796,746 · Granted May 7, 2019

Semiconductor device and method of manufacturing the same

Inventors: Eiji Hayashi (Tokyo, JP); Kyo Go (Tokyo, JP); Kozo Harada (Tokyo, JP); Shinji Baba (Tokyo, JP)
Assignee: Renesas Electronics Corporation
H01L23/49827H01L21/4853H01L21/563H01L21/6835H01L23/3142H01L23/3157H01L23/36H01L23/373H01L23/49811H01L23/49816H01L23/49822H01L23/49838H01L23/49894H01L23/562H01L24/11H01L24/16H01L24/29H01L24/32H01L24/743H01L24/81H05K3/4602H01L2021/6015H01L2224/05001H01L2224/056H01L2224/05008H01L2224/05009H01L2224/05022H01L2224/05023H01L2224/05024H01L2224/05025H01L2224/05124H01L2224/05572H01L2224/11003H01L2224/131H01L2224/13099H01L2224/16225H01L2224/16227H01L2224/2919H01L2224/29111H01L2224/32225H01L2224/73203H01L2224/73204H01L2224/73253H01L2224/81193H01L2224/81205H01L2224/81801H01L2224/81909H01L2224/83102H01L2224/92125H01L2924/014H01L2924/01005H01L2924/0105H01L2924/01006H01L2924/01013H01L2924/01018H01L2924/01019H01L2924/01022H01L2924/01029H01L2924/01033H01L2924/0133H01L2924/01074H01L2924/01078H01L2924/01082H01L2924/12042H01L2924/12044H01L2924/1306H01L2924/13091H01L2924/1579H01L2924/15174H01L2924/15184H01L2924/15311H01L2924/15312H01L2924/15724H01L2924/15747H01L2924/351H05K1/0366H05K2201/029
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Quick Facts
Patent No.
US 10,283,444
App. No.
15/796,746
Granted
May 7, 2019
Kind
B2
Abstract

Even when a stiffener is omitted, the semiconductor device which can prevent the generation of twist and distortion of a wiring substrate is obtained. As for a semiconductor device which has a wiring substrate, a semiconductor chip by which the flip chip bond was made to the wiring substrate, and a heat spreader adhered to the back surface of the semiconductor chip, and which omitted the stiffener for reinforcing a wiring substrate and maintaining the surface smoothness of a heat spreader, a wiring substrate has a plurality of insulating substrates in which a through hole whose diameter differs, respectively was formed, and each insulating substrate contains a glass cloth.

Claims (31)

1. A semiconductor device comprising:

a wiring substrate having a first insulating layer, a second insulating layer which is formed over a first top surface of the first insulating layer, a third insulating layer which is formed over a first bottom second main surface opposite the first top surface of the first insulating layer, and a plurality of wiring layers including a plurality of first wiring layers, a second wiring layer, and a third wiring layer;

a semiconductor chip having an obverse surface on which a plurality of bump electrodes are formed and a reverse surface opposite the obverse surface, the semiconductor chip being mounted over the second insulating layer of the wiring substrate such that the obverse surface faces the second insulating layer;

a sealing resin being disposed between the second insulating layer of the wiring substrate and the obverse surface of the semiconductor chip such that the sealing resin seals the plurality of bump electrodes; and

a plurality of external electrodes being disposed over the third insulating layer of the wiring substrate,

wherein the first insulating layer has the first top surface and the first bottom surface opposite the first top surface, and a plurality of first through electrodes which penetrate through the first insulating layer in a thickness direction of the first insulating layer,

wherein the plurality of first wiring layers are formed over the first top surface and the first bottom surface of the first insulating layer and are electrically connected each other via the plurality of first through electrodes, respectively,

wherein the second insulating layer has a second top surface and a second bottom surface opposite the second top surface, and a plurality of second through electrodes which penetrate through the second insulating layer in a thickness direction of the second insulating layer,

wherein the second wiring layer is formed over the second top surface of the second insulating layer and is electrically connected with the first wiring layers via the plurality of second through electrodes respectively,

wherein the third insulating layer has a third top surface and a third bottom surface opposite the third top surface, and a plurality of third through electrodes which penetrate through the third insulating layer in a thickness direction of the third insulating layer,

wherein the third wiring layer is formed over the third bottom surface of the third insulating layer and is electrically connected with the first wiring layers via the plurality of third through electrodes respectively,

wherein the first top surface of the first insulating layer faces the second bottom surface of the second insulating layer in a cross-section view,

wherein the first bottom surface of the first insulating layer faces the third top surface of the third insulating layer in the cross-section view,

wherein the first insulating layer includes a first glass cloth impregnated with insulating resin,

wherein the second insulating layer includes a second glass cloth impregnated with insulating resin,

wherein the third insulating layer includes a third glass cloth impregnated with insulating resin,

wherein each of the first, second, and third glass cloths is a woven glass fiber in a shape of a cloth,

wherein a thickness of each of the second and third insulating layers is different from a thickness of the first insulating layer in a thickness direction of the wiring substrate, and

wherein the first glass cloth is arranged between the first wiring layers in the cross-section view.

2. The semiconductor device according to claim 1 ,

wherein the second glass cloth is arranged between the first wiring layers and the second top surface of the second insulating layer in the cross-section view.

3. The semiconductor device according to claim 2 ,

wherein the third glass cloth is arranged between the first wirings and the third bottom surface of the third insulating layer in the cross section view.

4. The semiconductor device according to claim 3 ,

wherein a thickness of the second insulating layer is substantially equal to a thickness of the third insulating layer in the thickness direction of the wiring substrate.

5. The semiconductor device according to claim 4 ,

wherein each of the plurality of first, second, and third through electrodes is a through hole via, respectively.

6. A semiconductor device according to claim 5 ,

wherein the wiring substrate is a coreless substrate.

7. A semiconductor device according to claim 6 ,

wherein the first insulating substrate does not include a glass cloth without the first glass cloth in the cross-section view.

Priority Claims (2)
JP 2005-121063 · Apr 19, 2005 · national
JP 2006-096999 · Mar 31, 2006 · national
Continuity (14)
Continuation 15398444 · Jan 4, 2017
Continuation 15241777 · Aug 19, 2016
Continuation 15045978 · Feb 17, 2016
Continuation 14569423 · Dec 12, 2014
Continuation 14338175 · Jul 22, 2014
Continuation 14044497 · Oct 2, 2013
Division 13863241 · Apr 15, 2013
Continuation 13648876 · Oct 10, 2012
Continuation 13367029 · Feb 6, 2012
Continuation 13183196 · Jul 14, 2011
Division 12753521 · Apr 2, 2010
Division 12401193 · Mar 10, 2009
Division 11406337 · Apr 19, 2006
Related Publication 20180068936A1 · Mar 8, 2018