Compact three-dimensional memory device having a seal ring and methods of manufacturing the same
A semiconductor die includes a pair of first alternating stacks of first portions of insulating layers and electrically conductive layers located over a semiconductor substrate, groups of memory stack structures vertically extending through a respective one of the pair of the first alternating stacks, a pair of second alternating stacks of second portions of the insulating layers and dielectric material layers laterally adjoined to a respective one of the first alternating stacks, such that each second portion of the insulating layers is connected to a respective one of the first portions of the insulating layers, and at least one seal ring structure laterally enclosing, and laterally spaced from, the pair of first alternating stacks, and contacting at least a first sidewall of each of the pair of second alternating stacks.
1. A semiconductor die, comprising:
a pair of first alternating stacks of first portions of insulating layers and electrically conductive layers located over a semiconductor substrate;
groups of memory stack structures vertically extending through a respective one of the pair of the first alternating stacks, wherein each of the memory stack structures comprises a memory film and a vertical semiconductor channel laterally surrounded by the memory film;
a pair of second alternating stacks of second portions of the insulating layers and dielectric material layers laterally adjoined to a respective one of the first alternating stacks, wherein each second portion of the insulating layers is connected to a respective one of the first portions of the insulating layers; and
at least one seal ring structure laterally enclosing, and laterally spaced from, the pair of first alternating stacks, and contacting at least a first sidewall of each of the pair of second alternating stacks.
2. The semiconductor die of claim 1 , further comprising:
stepped surfaces of layers of the pair of first alternating stacks located in a respective terrace region; and
a set of contiguous dielectric material portions located between the pair of first alternating stacks and overlying the stepped surfaces of the pair of first alternating stacks.
3. The semiconductor die of claim 1 , wherein the at least one seal ring structure comprises a moat trench filled with a contact via structure which electrically contacts underlying lower interconnect structures.
4. The semiconductor die of claim 1 , further comprising a passivation dielectric layer comprising a diffusion-blocking material overlying each of the pair of first alternating stacks and the groups of memory stack structures, wherein the at least one seal ring structure extends from a top surface of the semiconductor substrate to a bottom surface of the passivation dielectric layer to provide a diffusion barrier structure for the semiconductor die.
5. The semiconductor die of claim 1 , wherein:
the semiconductor die comprises a monolithic three-dimensional NAND memory device;
the electrically conductive layers comprise, or are electrically connected to, a respective word line of the monolithic three-dimensional NAND memory device;
bottom ends of the memory stack structures contact a semiconductor material layer;
the memory stack structures comprise an array of monolithic three-dimensional NAND strings of the monolithic three-dimensional NAND memory device;
an integrated circuit comprising a driver circuit for monolithic three-dimensional NAND memory device is located on the semiconductor substrate;
the electrically conductive layers comprise a plurality of control gate electrodes having a strip shape extending substantially parallel to the top surface of the semiconductor substrate; and
the array of monolithic three-dimensional NAND strings comprises:
a plurality of semiconductor channels, wherein at least one end portion of each of the plurality of semiconductor channels extends substantially perpendicular to a top surface of the semiconductor substrate, and
a plurality of charge storage elements, each charge storage element located adjacent to a respective one of the plurality of semiconductor channels.
6. The semiconductor die of claim 1 , wherein the at least one sealing ring structure does not extend through a dummy staircase region.
7. A diced semiconductor chip, comprising the die of claim 1 .
8. The diced semiconductor chip of claim 7 , wherein:
the diced semiconductor chip comprises a pair of first die sidewalls and a pair of second die sidewalls that are perpendicular to the pair of first die sidewalls; and
the at least one seal ring structure comprises first linear sections that laterally extend parallel to the pair of first die sidewalls and second linear sections that laterally extend parallel to the pair of second die sidewalls.
9. The semiconductor die of claim 2 , wherein a first linear section of the least one seal ring structure contacts the first sidewall of each of the pair of second alternating stacks and does not contact the set of contiguous dielectric material portions, and a second linear section of the at least one seal ring structure contacts the set of contiguous dielectric material portions.
10. The semiconductor die of claim 2 , wherein a first linear section of the least one seal ring structure contacts the first sidewall of each of the pair of second alternating stacks and does not contact the set of contiguous dielectric material portions, and a second linear section of the at least one seal ring structure contacts a second sidewall of each of the pair of second alternating stacks and does not contact the set of contiguous dielectric material portions.
11. The semiconductor die of claim 4 , further comprising:
semiconductor devices located on a top surface of the semiconductor substrate;
lower interconnect level dielectric layers located over the semiconductor devices and embedding lower interconnect structures that are electrically connected to a respective one of the semiconductor devices, wherein the pair of first alternating stacks, the groups of memory stack structures, and the pair of second alternating stacks are located above the lower interconnect level dielectric layers; and
upper interconnect level dielectric layers located over the pair of first alternating stacks, the groups of memory stack structures, and the pair of second alternating stacks and embedding upper interconnect structures and underlying the passivation dielectric layer.
12. The semiconductor chip of claim 8 , wherein a continuous interface between the at least one seal ring structure and one of the second alternating stacks extends parallel to the pair of first die sidewalls for a lateral distance that is greater than 80% of a maximum lateral distance of each of the first die sidewalls, and extends parallel to the pair of second die sidewalls for a lateral distance that is less than 50% of a maximum lateral distance of each of the second die sidewalls.
13. The semiconductor chip of claim 8 , wherein a continuous interface between the at least one seal ring structure and one of the second alternating stacks extends parallel to the pair of first die sidewalls for a lateral distance that is greater than 99% of a maximum lateral distance of each of the first die sidewalls, and extends in proximity to, and parallel to, each of the pair of second die sidewalls for a lateral distance that is less than 50% of a maximum lateral distance of each of the second die sidewalls.
14. A method of manufacturing a semiconductor die, comprising:
forming a vertically alternating sequence of continuous insulating layers and continuous dielectric material layers having a different composition than the continuous insulating layers over a semiconductor substrate;
patterning the vertically alternating sequence such that patterned portions of the vertically alternating sequence comprise a pair of in-process alternating stacks of insulating layers and dielectric material layers and such that stepped surfaces of layers of the pair of in-process alternating stacks are provided in a respective terrace region;
forming a set of contiguous dielectric material portions between the pair of in-process alternating stacks and over the stepped surfaces of the pair of first alternating stacks;
forming groups of memory stack structures vertically extending through the pair of in-process alternating stacks, wherein each of the memory stack structures comprises a memory film and a vertical semiconductor channel laterally surrounded by the memory film;
replacing portions of the dielectric material layers in the pair of in-process alternating stacks with electrically conductive layers, wherein the pair of in-process alternating stacks is converted into a pair of first alternating stacks of first portions of the insulating layers and the electrically conductive layers and including respective stepped surfaces in the terrace regions, and a pair of second alternating stacks of second portions of the insulating layers and remaining portions of dielectric material layers laterally adjoined to a respective one of the first alternating stacks, wherein each second portion of the insulating layers is connected to a respective one of the first portions of the insulating layers; and
forming at least one seal ring structure through the pair of second alternating stacks, and surrounding of the pair of first alternating stacks.
15. The method of claim 14 , further comprising dicing through the pair of second alternating stacks and through the semiconductor substrate to provide diced structures, wherein each of the diced structures comprises a semiconductor chip.
16. The method of claim 15 , further comprising forming a passivation dielectric layer comprising a diffusion-blocking material over an entire area of the semiconductor die prior to the dicing, wherein the at least one seal ring structure extends from a top surface of the semiconductor substrate to a bottom surface of the passivation dielectric layer to provide a diffusion barrier structure for the semiconductor chip.
17. The method of claim 15 , wherein:
the semiconductor chip has a rectangular shape in a plan view;
the semiconductor chip comprises a pair of first die sidewalls and a pair of second die sidewalls that are perpendicular to the pair of first die sidewalls;
the at least one seal ring structure includes first linear sections that laterally extend parallel to the pair of first die sidewalls and second linear sections that laterally extend parallel to the pair of second die sidewalls; and
each first linear section of one of the at least one seal ring structure contacts a sidewall of a respective one of the pair of second alternating stacks.
18. The method of claim 17 , wherein a second linear section of the at least one seal ring structure contacts another sidewall of each of the pair of second alternating stacks.
19. The method of claim 17 , wherein a second linear section of the at least one seal ring structure contacts the set of contiguous dielectric material portions, and does not contact the pair of second alternating stacks.
20. The method of claim 16 , further comprising:
forming semiconductor devices on a top surface of the semiconductor substrate;
forming lower interconnect level dielectric layers embedding lower interconnect structures that are electrically connected to a respective one of the semiconductor devices over the semiconductor devices, wherein the pair of first alternating stacks, the groups of memory stack structures, the set of contiguous dielectric material portions, and the pair of second alternating stacks are formed above the lower interconnect level dielectric layers; and
forming upper interconnect level dielectric layers located over the pair of first alternating stacks, the groups of memory stack structures, the set of contiguous dielectric material portions, and the pair of second alternating stacks and embedding upper interconnect structures, wherein the passivation dielectric layer is formed over the upper interconnect level dielectric layers.