High bandwidth chip-to-chip interface using HBM physical interface
Techniques related to a high bandwidth interface (HBI) for communication between multiple host devices on an interposer are described. In an example, the HBI repurposes a portion of the high bandwidth memory (HBM) interface, such as the physical layer. A computing system is provided. The computing system includes a first host device and at least a second host device. The first host device is a first die on an interposer and the second host device is a second die on the interposer. The first host device and the second host device are interconnected via at least one HBI. The HBI implements a layered protocol for communication between the first host device and the second host device. The layered protocol includes a physical layer protocol that is configured according to a HBM physical layer protocol.
1. A computing system, comprising:
a first host device comprising a first die on an interposer; and
at least one second host device comprising a second die on the interposer, wherein:
the first host device and the at least one second host device are interconnected via at least one high bandwidth interface (HBI) that implements a layered protocol for communication between the first host device and the at least one second host device, the layered protocol includes a physical layer protocol that is configured according to a high bandwidth memory (HBM) physical layer protocol.
2. The computing system of claim 1 , wherein the first and second host devices are each configurable as a master device, a slave device, or both.
3. The computing system of claim 1 , wherein the HBI provides a plurality of independent directional channels.
4. The computing system of claim 1 , wherein the first host device comprises a 3D programmable integrated circuit (1C), and wherein the at least one second host device comprises an application-specific 1C (ASIC).
5. The computer system of claim 1 , wherein the physical layer protocol is configured in a continuous data flow per input/output (I/O) word mode and a 4:1 serializer/deserializer (SERDES) mode.
6. The computer system of claim 1 , wherein the layered protocol further includes a transport layer protocol including an output channel configured to issue credits used by an input channel of the transport layer protocol.
7. The computer system of claim 1 , wherein the layered protocol further includes a protocol layer comprising a high-level streaming or memory-mapped advanced extensible interface (AXI) protocol.
8. The computer system of claim 7 , wherein the memory-mapped AXI protocol includes a 10-bit write strobe signal, wherein a first 5 bits indicate a number of zeros in a first region of the write strobe in which all bits are zero, wherein a second 5 bits indicate a number of ones in a second region of the write strobe in which all bits are one, and wherein the write strobe further comprises a third region in which all bits are zero.
9. The computer system of claim 7 , wherein the memory-mapped AXI protocol supports a mixed command channel packet for a simultaneous read command and write command.
10. The computer system of claim 7 , wherein the memory-mapped AXI protocol supports a mixed response channel packet for a simultaneous read response and write response.
11. The computer system of claim 1 , wherein the first die and the die are connected via a plurality of wires, wherein bumps on the first die are connected to bumps in a corresponding location on the second die, wherein the transport layer is further configured to reorder bits, and wherein the first die and the second die have a same orientation or a different orientation with respect to each other on the interposer.
12. A method for communication between devices on an interposer, comprising:
sending at least a first signal from a first device on the interposer to a second device on the interposer via a high bandwidth interface (HBI), wherein sending the first signal via the HBI comprises sending the first signal using a layered protocol including a physical layer protocol that is configured according to a high bandwidth memory (HBM) physical layer protocol; and
receiving at least a second signal from the second device on the interposer via the HBI.
13. The method of claim 12 , wherein the first signal is sent via a first independent directional HBI channel, and wherein the second signal is received via a second directional HBI channel.
14. The method of claim 12 , wherein the first device comprises a 3D programmable integrated circuit (IC), and wherein the second device comprises an application-specific IC (ASIC).
15. The method of claim 12 , wherein the physical layer protocol is configured in a continuous data flow per input/output (I/O) word mode and a 4:1 serializer/deserializer (SERDES) mode.
16. The method of claim 12 , wherein the layered protocol further includes a transport layer protocol including an output channel configured to issue credits used by an input channel of the transport layer protocol.
17. The method of claim 12 wherein the layered protocol further includes a protocol layer comprising a high-level streaming or memory-mapped advanced extensible interface (AXI) protocol.
18. The method of claim 17 , wherein the first or second signal comprises a 10-bit write strobe signal, wherein a first 5 bits indicate a number of zeros in a first region of the write strobe in which all bits are zero, wherein a second 5 bits indicate a number of ones in a second region of the write strobe in which all bits are one, and wherein the write strobe further comprises a third region in which all bits are zero.
19. The method of claim 17 , wherein the first or second signal comprises a mixed command channel packet for a simultaneous read command and write command.
20. The method of claim 17 , wherein the first or second signal comprises a mixed response channel packet for a simultaneous read response and write response.