3D semiconductor device and structure with metal layers
A semiconductor device, the device including: a first silicon layer including a first single crystal silicon; a first metal layer over the first silicon layer; a second metal layer over the first metal layer; a first level including a plurality of transistors over the second metal layer, where the plurality of transistors include a second single crystal silicon; a third metal layer over the first level; a fourth metal layer over the third metal layer, where the fourth metal layer is aligned to the first metal layer with less than 40 nm alignment error; and a via disposed through the first level, where the via has a diameter of less than 450 nm.
1. A semiconductor device, the device comprising:
a first silicon layer comprising a first single crystal silicon;
a first metal layer over said first silicon layer;
a second metal layer over said first metal layer;
a first level comprising a plurality of transistors, said first level over said second metal layer,
wherein said plurality of transistors comprise a second single crystal silicon;
a third metal layer over said first level;
a fourth metal layer over said third metal layer,
wherein said fourth metal layer is aligned to said first metal layer with less than 40 nm alignment error; and
a via disposed through said first level,
wherein said via has a diameter of less than 450 nm.
2. The device according to claim 1 ,
wherein said via comprises tungsten.
3. The device according to claim 1 ,
wherein said first level thickness is less than two microns.
4. The device according to claim 1 , further comprising:
connection pads disposed over portions of said fourth metal layer,
wherein said connection pads are capable to provide connections to external devices.
5. The device according to claim 1 , further comprising:
a global power distribution network and a local power distribution network,
wherein said global power distribution network comprises said fourth metal layer, and
wherein said local power distribution network comprises said third metal layer.
6. The device according to claim 1 ,
wherein at least one of said transistors comprise a two sided gate.
7. The device according to claim 1 , further comprising:
oxide to oxide bonds.
8. A semiconductor device, the device comprising:
a first silicon layer comprising first single crystal silicon;
a first metal layer over said first silicon layer;
a second metal layer over said first metal layer;
a first level comprising a plurality of transistors, said first level over said second metal layer,
wherein said plurality of transistors comprise second single crystal silicon;
a third metal layer over said first level;
a fourth metal layer over said third metal layer,
wherein said fourth metal layer is aligned to said first metal layer with less than 40 nm alignment error; and
a via disposed through said first level,
wherein said via comprises tungsten.
9. The device according to claim 8 ,
wherein said via has a diameter of less than 450 nm.
10. The device according to claim 8 ,
wherein said first level has a thickness of less than two microns.
11. The device according to claim 8 , further comprising:
connection pads over a portion of said fourth metal layer,
wherein said connection pads are capable to provide connection to external devices.
12. The device according to claim 8 , further comprising:
a global power distribution network and a local power distribution network
wherein said global power distribution network comprises said fourth metal layer, and
wherein said local power distribution network comprises said third metal layer.
13. The device according to claim 8 ,
wherein at least one of said transistors comprises a two sided gate.
14. The device according to claim 8 , further comprising:
oxide to oxide bonds.
15. A semiconductor device, the device comprising:
a first silicon layer comprising first single crystal silicon;
a first metal layer over said first silicon layer;
a second metal layer over said first metal layer;
a first level comprising a plurality of transistors, said first level over said second metal layer,
wherein said plurality of transistors comprise second single crystal silicon;
a third metal layer over said first level;
a fourth metal layer over said third metal layer,
wherein said fourth metal layer is aligned to said first metal layer with less than 40 nm alignment error;
a global power distribution network and a local power distribution network,
wherein said global power distribution network comprises said fourth metal layer, and
wherein said local power distribution network comprises said third metal layer.
16. The device according to claim 15 , further comprising:
a via disposed through said first level,
wherein said via comprises tungsten.
17. The device according to claim 15 ,
wherein said first level has a thickness of less than two microns.
18. The device according to claim 15 , further comprising:
connection pads disposed over said fourth metal layer,
wherein said connection pads are capable to provide connection to external devices.
19. The device according to claim 15 ,
wherein at least one of said transistors comprise a two sided gate.
20. The device according to claim 15 , further comprising:
a via through said first level,
wherein said via has a diameter of less than 450 nm.