Granted Patent B2

US 12,205,522 · App. 17/677,857 · Granted Jan 21, 2025

Inventors: Thorsten Baumheinrich (Altdorf, DE); Peter Brick (Regensburg, DE); Jean-Jacques Drolet (Obertraubling, DE); Hubert Halbritter (Dietfurt Toeging, DE); Laura Kreiner (Regensburg, DE); Jens Richter (Hemau, DE); Thomas Schwarz (Regensburg, DE); Paul Ta (Fremont, CA); Kilian Regau (Regensburg, DE); Christopher Soell (Veitsbronn, DE); Hoa Vu (Milpitas, CA); Christopher Wiesmann (Barbing, DE); Patrick Hoerner (Regensburg, DE); Jong Park (Sunnyvale, CA); Kanishk Chand (Santa Clara, CA)

Assignee: OSRAM OPTO SEMICONDUCTORS GMBH

G09G3/32B60K35/00G09G5/10B60K35/22B60K2360/1523B60K2360/349G09G2320/0633

Abstract

Claims (14)

1. A display matrix control circuit for controlling a plurality of light emitting devices arranged in rows and columns, comprising:

a row selection input for a row selection signal and a column data input for a data signal;

a ramp signal input for a ramp signal having a level between a first value and a second value and a trigger input for a trigger signal;

a column data buffer configured to buffer the data signal in response to the row selection signal; and

a pulse generator coupled to the column data buffer via a first input and to the ramp signal input via a second input, the pulse generator being configured to provide a buffered output signal to control an on/off ratio of at least one of said plurality of light emitting devices in response to the trigger signal, the data signal, and the ramp signal,

wherein the pulse generator comprises:

a comparator device for comparing the buffered data signal with the ramp signal; and

an RS Flip-Flop having a R-input coupled directly to an output of the comparator device and a S-input receiving the trigger signal.

2. The display matrix control circuit according to claim 1 , wherein the column data buffer comprises a capacitor for storing the data signal and a switch disposed between the capacitor and the column data input.

3. The display matrix control circuit according to claim 1 , wherein the comparator device comprises a power control input coupled to the trigger input to adjust its power consumption based on the trigger signal.

4. The display matrix control circuit according to claim 1 , wherein the comparator device is coupled to the output buffer to control its power consumption based on an output state of the output buffer.

5. The display matrix control circuit according to claim 1 , wherein the column data buffer is coupled with an inverting input of the comparator device and the ramp signal input is coupled with an non-inverting input of the comparator device.

6. The display matrix control circuit according to claim 1 , further comprising a ramp generator for supplying the ramp signal to the ramp signal input, the ramp generator being configured to generate a signal varying between an initial value and a final value in response to the trigger signal.

7. The display matrix control circuit according to claim 1 for use in a p-display or for driving a p-LED, p-LED array, or an array of p-LEDS, the display matrix control circuit configured for controlling the plurality of light emitting devices arranged in rows and columns.

Assignments (1)

Priority Claims (7)

Continuity (4)

References Cited (346)