Package comprising a substrate and an interconnection die configured for high density interconnection
A package comprising a substrate comprising a first surface and a second surface; a first integrated device coupled to the first surface of the substrate; an interconnection die coupled to the first surface of the substrate; a first encapsulation layer coupled to the first surface of the substrate, wherein the first encapsulation layer encapsulates the first integrated device and the interconnection die; and a second integrated device coupled to the second surface of the substrate.
1 . A package comprising:
a substrate comprising a first surface and a second surface;
a first integrated device coupled to the first surface of the substrate;
an interconnection die coupled to the first surface of the substrate through a first plurality of solder interconnects,
wherein the first plurality of solder interconnects are coupled to and touching (i) a first side of the interconnection die and (ii) the substrate,
wherein the first side of the interconnection die faces in a direction of the substrate, and
wherein the interconnection die includes a pad die interconnect;
a second plurality of solder interconnects coupled to and touching a second side of the interconnection die, wherein the second side of the interconnection die is opposite to the first side of the interconnection die;
a first encapsulation layer coupled to the first surface of the substrate,
wherein the first encapsulation layer at least partially encapsulates the first integrated device, the interconnection die, and the pad die interconnect; and
a second integrated device coupled to the second surface of the substrate.
2 . The package of claim 1 , wherein the interconnection die comprises:
a die substrate; and
a plurality of die interconnects including:
a via die interconnect that extends vertically through the entire die substrate; and
the pad die interconnect coupled to the via die interconnect.
3 . The package of claim 2 , wherein two neighboring die interconnects from the plurality of die interconnects have a pitch in a range of 150-270 micrometers.
4 . The package of claim 2 , wherein the interconnection die has a thickness in a range of 100-200 micrometers.
5 . The package of claim 2 ,
wherein the interconnection die includes a plurality of pad die interconnects comprising the pad die interconnect,
wherein the plurality of die interconnects include a plurality of via interconnects comprising the via die interconnect, and
wherein the plurality of pad die interconnects are coupled to and touch the first plurality of solder interconnects.
6 . The package of claim 2 , wherein the die substrate includes glass and/or silicon.
7 . The package of claim 1 , further comprising a second encapsulation layer coupled to the second surface of the substrate.
8 . The package of claim 7 , further comprising an outer metal layer coupled to the second encapsulation layer.
9 . The package of claim 1 , wherein the first integrated device includes a first chiplet and the second integrated device includes a second chiplet.
10 . The package of claim 1 , wherein the interconnection die is located laterally to the first integrated device.
11 . The package of claim 1 , wherein the first integrated device includes a first chiplet and the second integrated device includes a second chiplet.
12 . A device comprising:
a package comprising:
a substrate comprising a first surface and a second surface;
a first integrated device coupled to the first surface of the substrate;
an interconnection die coupled to the first surface of the substrate through a first plurality of solder interconnects,
wherein the first plurality of solder interconnects are coupled to and touching (i) a first side of the interconnection die and (ii) the substrate,
wherein the first side of the interconnection die faces in a direction of the substrate, and
wherein the interconnection die includes a pad die interconnect;
a second plurality of solder interconnects coupled to and touching a second side of the interconnection die, wherein the second side of the interconnection die is opposite to the first side of the interconnection die;
a first encapsulation layer coupled to the first surface of the substrate,
wherein the first encapsulation layer at least partially encapsulates the first integrated device, the interconnection die, and the pad die interconnect; and
a second integrated device coupled to the second surface of the substrate.
13 . The device of claim 12 , wherein the interconnection die comprises:
a die substrate; and
a plurality of die interconnects including:
a via die interconnect that extends vertically through the entire die substrate; and
the pad die interconnect coupled to the via die interconnect.
14 . The device of claim 13 , wherein two neighboring die interconnects from the plurality of die interconnects have a pitch in a range of 150-270 micrometers.
15 . The device of claim 13 , wherein the interconnection die has a thickness in a range of 100-200 micrometers.
16 . The device of claim 13 ,
wherein the interconnection die includes a plurality of pad die interconnects comprising the pad die interconnect,
wherein the plurality of die interconnects include a plurality of via die interconnects comprising the via die interconnect, and
wherein the plurality of pad die interconnects are coupled to and touch the first plurality of solder interconnects.
17 . The device of claim 13 , wherein the die substrate includes glass and/or silicon.
18 . The device of claim 12 , further comprising a second encapsulation layer coupled to the second surface of the substrate.
19 . The device of claim 18 , further comprising an outer metal layer coupled to the second encapsulation layer.
20 . The device of claim 12 , wherein the first integrated device includes a first chiplet and the second integrated device includes a second chiplet.
21 . The device of claim 12 ,
wherein the interconnection die is located laterally to the first integrated device,
wherein the device further comprises a board coupled to the package through the second plurality of solder interconnects.
22 . The device of claim 12 , wherein the first integrated device includes a first chiplet and the second integrated device includes a second chiplet.
23 . The device of claim 12 , wherein the device is selected from a group consisting of a music player, a video player, an entertainment unit, a navigation device, a communications device, a mobile device, a mobile phone, a smartphone, a personal digital assistant, a fixed location terminal, a tablet computer, a computer, a wearable device, a laptop computer, a server, an internet of things (IoT) device, and a device in an automotive vehicle.
24 . A method for fabricating a package, comprising:
providing a substrate comprising a first surface and a second surface;
coupling a first integrated device to the first surface of the substrate;
coupling an interconnection die to the first surface of the substrate through a first plurality of solder interconnects,
wherein the first plurality of solder interconnects are coupled to and touching (i) a first side of the interconnection die and (ii) the substrate,
wherein the first side of the interconnection die faces in a direction of the substrate,
wherein a second plurality of solder interconnects are coupled to and touching a second side of the interconnection die,
wherein the second side of the interconnection die is opposite to the first side of the interconnection die,
wherein the interconnection die includes a pad die interconnect;
coupling a first encapsulation layer to the first surface of the substrate, wherein the first encapsulation layer at least partially encapsulates the first integrated device, the interconnection die, and the pad die interconnect; and
coupling a second integrated device to the second surface of the substrate.
25 . The method of claim 24 , wherein the interconnection die comprises:
a die substrate; and
a plurality of die interconnects including:
a via die interconnect that extends vertically through the entire die substrate; and
the pad die interconnect coupled to the via die interconnect.
26 . The method of claim 25 , wherein two neighboring die interconnects from the plurality of die interconnects have a pitch in a range of about 150-270 micrometers.
27 . The method of claim 25 , wherein the interconnection die has a thickness in a range of about 100-200 micrometers.
28 . The method of claim 25 ,
wherein the interconnection die includes a plurality of pad die interconnects comprising the pad die interconnect,
wherein the plurality of die interconnects include a plurality of via die interconnects comprising the via die interconnect, and
wherein the plurality of pad die interconnects are coupled to and touch the first plurality of solder interconnects.
29 . The method of claim 25 , wherein the die substrate includes glass and/or silicon.
30 . The method of claim 24 , further comprising coupling a second encapsulation layer to the second surface of the substrate.