Semiconductor device
A semiconductor device includes: a first multi-gate field effect transistor (FET) disposed over a substrate, the first multi-gate FET including a first active region; and a second multi-gate FET disposed over the first multi-gate FET, the second multi-gate FET including a second active region. The first active region and the second active region are not fully projected in a vertical direction perpendicular to the substrate.
1 . A semiconductor device, comprising:
a first multi-gate field effect transistor (FET) disposed over a substrate, the first multi-gate FET including a first active region extending on a first horizontal plane; and
a second multi-gate FET disposed over the first multi-gate FET, the second multi-gate FET including a second active region extending on a second horizontal plane parallel to the first horizontal plane;
wherein the first multi-gate FET further includes a first metal contact region disposed over the first active region and a second metal contact region disposed over the first active region;
wherein the second multi-gate FET further includes a third metal contact region disposed over the second active region and a fourth metal contact region disposed over the second active region; and
wherein the first metal contact region and the third metal contact region do not fully overlap when viewed from a vertical direction, and the second metal contact region and the fourth metal contact region do not fully overlap when viewed from the vertical direction.
2 . The semiconductor device of claim 1 , wherein the first active region and the second active region have different conductivity types from each other.
3 . The semiconductor device of claim 1 , wherein a first projection of the second active region on the first horizontal plane partially overlaps with the first active region.
4 . The semiconductor device of claim 1 , wherein a first projection of the second active region on the first horizontal plane and the first active region do not overlap.
5 . The semiconductor device of claim 1 , wherein a first area of the first active region is smaller than a second area of the second active region.
6 . The semiconductor device of claim 1 , wherein a first area of the first active region is equal to a second area of the second active region.
7 . The semiconductor device of claim 1 , wherein a first area of the first active region is larger than a second area of the second active region.
8 . The semiconductor device of claim 1 , wherein the second metal contact region and the third metal contact region do not fully overlap when viewed from the vertical direction.
9 . The semiconductor device of claim 1 , wherein the first multi-gate FET includes a first gate region adjacent to a plurality of side surfaces of the first active region, and the second multi-gate FET includes a second gate region adjacent to a plurality of side surfaces of the second active region.
10 . The semiconductor device of claim 9 , wherein the first gate region and the second gate region are separate.
11 . The semiconductor device of claim 9 , wherein the first gate region and the second gate region are connected.
12 . The semiconductor device of claim 1 , wherein a first width of the first active region is equal to a second width of the second active region.
13 . The semiconductor device of claim 1 , wherein a first width of the first active region is different from a second width of the second active region.
14 . A semiconductor device, comprising:
a first multi-gate field effect transistor (FET) disposed over a substrate, the first multi-gate FET including a first active region extending on a first horizontal plane; and
a second multi-gate FET disposed over the first multi-gate FET, the second multi-gate FET including a second active region extending on a second horizontal plane parallel to the first horizontal plane;
wherein the first active region and the second active region do not fully overlap when viewed from a vertical direction perpendicular to the first horizontal plane, and
wherein the first multi-gate FET includes a first metal contact region disposed over the first active region and a second metal contact region disposed over the first active region and the second multi-gate FET includes a third metal contact region disposed over the second active region and a fourth metal contact region disposed over the second active region, the first metal contact region and the third metal contact region do not fully overlap when viewed from a vertical direction, and the second metal contact region and the fourth metal contact region do not fully overlap when viewed from the vertical direction.
15 . The semiconductor device of claim 1 , wherein the second metal contact region and the fourth metal contact region do not fully overlap when viewed from the vertical direction.
16 . The semiconductor device of claim 14 , wherein a first projection of the second active region on the first horizontal plane partially overlaps with the first active region.
17 . The semiconductor device of claim 14 , wherein a first projection of the second active region on the first horizontal plane and the first active region do not overlap.
18 . A semiconductor device, comprising:
a first multi-gate field effect transistor (FET) disposed over a substrate, the first multi-gate FET including a first active region extending on a first horizontal plane, a first metal contact region disposed over the first active region, and a second metal contact region disposed over the first active region; and
a second multi-gate FET disposed over the first multi-gate FET, the second multi-gate FET including a second active region extending on a second horizontal plane parallel to the first horizontal plane, a third metal contact region disposed over the second active region, and a fourth metal contact region disposed over the second active region;
wherein the first active region and the second active region do not fully overlap when viewed from a vertical direction perpendicular to the first horizontal plane, the first metal contact region and the third metal contact region do not fully overlap when viewed from a vertical direction, and the second metal contact region and the fourth metal contact region do not fully overlap when viewed from the vertical direction.
19 . The semiconductor device of claim 18 , wherein the second metal contact region and the third metal contact region do not fully overlap when viewed from the vertical direction.
20 . The semiconductor device of claim 18 , wherein the first multi-gate FET includes a first gate region adjacent to a plurality of side surfaces of the first active region, and the second multi-gate FET includes a second gate region adjacent to a plurality of side surfaces of the second active region.