Methods used in forming a memory array comprising strings of memory cells including selective depositing of silicon
A method used in forming a memory array comprising strings of memory cells comprises forming a conductor tier comprising conductor material on a substrate. A vertical stack comprising alternating first tiers and second tiers is formed above the conductor tier. Channel-material strings extend through the alternating tiers. Conducting material is formed in a lower of the first tiers that directly electrically couples together the channel material of individual of the channel-material strings and the conductor material of the conductor tier. The forming of the conducting material comprises forming conductive material in the lower first tier against the channel material of the individual channel-material strings. The conductive material comprises an upper portion and a lower portion having a void-space vertically there-between. The void-space comprises an exposed silicon-containing surface. Silicon is selectively deposited into the void-space onto and from the exposed silicon-containing surface. Other embodiments, including structure independent of method, are disclosed.
1 . A method used in forming a memory array comprising strings of memory cells, comprising:
forming a conductor tier comprising conductor material on a substrate;
forming laterally-spaced memory-block regions individually comprising a vertical stack comprising alternating first tiers and second tiers directly above the conductor tier, channel-material strings extending through the first tiers and the second tiers; and
forming conducting material in a lower of the first tiers that directly electrically couples together the channel material of individual of the channel-material strings and the conductor material of the conductor tier, the forming of the conducting material comprising:
forming conductive material in the lower first tier in the laterally-spaced-memory-block regions against the channel material of the individual channel-material strings, the conductive material comprising an upper portion and a lower portion in the laterally-spaced-memory-block regions and having a void-space in the laterally-spaced-memory-block regions vertically between the upper and lower portions, the void-space comprising an exposed elemental-silicon-containing surface in the laterally-spaced-memory-block regions; and
selectively depositing silicon into the void-space in the laterally-spaced-memory-block regions onto and from the exposed elemental-silicon-containing surface and not onto exposed non-elemental-silicon-containing surfaces, the selectively-deposited silicon completely filling the void-space in the laterally-spaced-memory-block regions.
2 . The method of claim 1 wherein the upper portion, the lower portion, and the exposed silicon-containing surface comprise conductively-doped polysilicon.
3 . The method of claim 1 wherein the silicon-containing surface on and from which the silicon is selectively deposited comprises a floor of the void-space.
4 . The method of claim 1 wherein the silicon-containing surface on and from which the silicon is selectively deposited comprises a ceiling of the void-space.
5 . The method of claim 1 wherein the silicon-containing surface on and from which the silicon is selectively deposited comprises a lateral sidewall of the void-space.
6 . The method of claim 1 wherein the silicon-containing surface on and from which the silicon is selectively deposited comprises a floor of the void-space, a ceiling of the void-space, and a lateral sidewall of the void-space.
7 . The method of claim 1 wherein the first tiers are conductive tiers in a finished circuitry construction and the second tiers are insulative tiers in the finished circuitry construction, the void-space being in a lowest of the conductive tiers.
8 . The method of claim 1 wherein the selectively depositing is of epitaxial silicon.
9 . The method of claim 1 wherein the selectively depositing is of polysilicon.
10 . The method of claim 1 wherein the selectively depositing is of amorphous silicon and further comprising annealing the amorphous silicon to form polysilicon therefrom.
11 . The method of claim 1 wherein,
the conductive material is crystalline in a finished circuitry construction; and
the selectively-deposited silicon in the finished circuitry construction is crystalline and has an average maximum-straight-line distance across individual of its crystal grains that is at least 20% greater than an average maximum-straight-line distance across individual crystal grains of the crystalline conductive material.
12 . The method of claim 11 wherein the average maximum-straight-line distance across the individual crystal grains of the selectively-deposited silicon in the finished circuitry construction is no more than 10,000% greater than the average maximum-straight-line distance across the individual crystal grains of the crystalline conductive material.
13 . The method of claim 1 wherein the selectively-deposited silicon is conductive at least in a finished circuitry construction.
14 . A method used in forming a memory array comprising strings of memory cells, comprising:
forming a conductor tier comprising conductor material on a substrate;
forming laterally-spaced memory-block regions individually comprising a vertical stack comprising alternating first tiers and second tiers directly above the conductor tier, channel-material strings extending through the first tiers and the second tiers; and
forming conducting material in a lower of the first tiers that directly electrically couples together the channel material of individual of the channel-material strings and the conductor material of the conductor tier, the forming of the conducting material comprising:
forming undoped semiconductive material in the lower first tier directly against the channel material of the individual channel-material strings, the undoped semiconductive material having more than 0 atomic dopant concentration and less than 0.01 atomic percent dopant therein;
forming conductive material in the lower first tier directly against the undoped semiconductive material, the conductive material comprising an upper portion and a lower portion having a void-space vertically there-between, the void-space comprising an exposed elemental-silicon-containing surface; and
selectively depositing silicon into the void-space onto and from the exposed elemental-silicon-containing surface.
15 . The method of claim 14 wherein the undoped semiconductive material comprises polysilicon.
16 . The method of claim 14 wherein the undoped semiconductive material has 1×10 7 atoms/cm 3 of dopant therein.
17 . The method of claim 14 wherein the undoped semiconductive material is not intrinsically conductive in a finished construction of the memory array, yet is sufficiently thin such that electrical conduction occurs there-through as a result of such thinness.
18 . The method of claim 17 wherein the undoped semiconductive material forms ohmic contact with the conductive material and with the channel material.
19 . The method of claim 14 wherein the initially-formed undoped semiconductive material becomes and is intrinsically conductive in a finished construction of the memory array.