Crystalline oxide semiconductor memory device
View Patent ↗A novel semiconductor device is provided. The semiconductor device includes an oxide semiconductor as a first semiconductor, silicon as a second semiconductor, and a plurality of memory cells lined up in a first direction; and a memory cell includes a writing transistor and a reading transistor. The first semiconductor and the second semiconductor extend in the first direction, part of the first semiconductor functions as a channel formation region of the writing transistor, and part of the second semiconductor functions as a channel formation region of the reading transistor. The second semiconductor includes a region in contact with a first layer containing a first metal element.
1 . A semiconductor device comprising:
a structural body extending in a first direction;
a plurality of first conductors extending in a second direction that intersects with the first direction; and
a plurality of second conductors extending in the second direction,
wherein the structural body comprises:
a third conductor;
a first insulator;
a plurality of fourth conductors;
a first semiconductor;
a second insulator;
a second semiconductor; and
a third insulator,
wherein, in a first region corresponding to each intersecting portion of the plurality of first conductors and the structural body, the first insulator, the first semiconductor, the second insulator, the second semiconductor, and the third insulator are arranged concentrically in that order around the third conductor,
wherein, in the first region, a first portion of one of the plurality of first conductors is configured to function as a first gate electrode of a first transistor, a first portion of the first semiconductor is configured to function as a first channel formation region of the first transistor, and a first portion of the third conductor is configured to function as a second gate electrode of the first transistor
wherein, in a second region corresponding to each intersecting portion of the plurality of second conductors and the structural body, the first insulator, one of the plurality of fourth conductors, the first semiconductor, the second insulator, the second semiconductor, and the third insulator are arranged concentrically in that order around the third conductor and the one of the plurality of fourth conductors is in contact with the first semiconductor,
wherein, in the second region, a first portion of one of the plurality of second conductors is configured to function as a first gate electrode of a second transistor, a first portion of the second semiconductor is configured to function as a second channel formation region of the second transistor, and a first portion of the one of the plurality of fourth conductors is configured to function as a second gate electrode of the second transistor,
wherein the first semiconductor comprises an oxide semiconductor,
wherein the second semiconductor comprises silicon,
wherein the second semiconductor comprises a region in contact with a first layer, and
wherein the first layer comprises a first metal element.
2 . The semiconductor device according to claim 1 , wherein the first metal element is nickel.
3 . The semiconductor device according to claim 1 , wherein the first layer comprises an impurity element.
4 . The semiconductor device according to claim 3 , wherein the impurity element is phosphorus.
5 . The semiconductor device according to claim 1 , wherein the oxide semiconductor comprises at least one of indium and zinc.
6 . The semiconductor device according to claim 1 , wherein the oxide semiconductor comprises CAAC-OS, nc-OS, or a-like OS.
7 . A semiconductor device comprising:
a structural body extending in a first direction;
a plurality of first conductors extending in a second direction that intersects with the first direction; and
a plurality of second conductors extending in the second direction,
wherein the structural body comprises:
a third conductor;
a first insulator;
a plurality of fourth conductors;
a first semiconductor;
a second insulator;
a second semiconductor; and
a third insulator,
wherein, in a first region corresponding to each intersecting portion of the plurality of first conductors and the structural body, the first insulator, the first semiconductor, the second insulator, the second semiconductor, and the third insulator are arranged concentrically in that order on the outside of the third conductor,
wherein, in the first region, a first portion of one of the plurality of first conductors is configured to function as a first gate electrode of a first transistor, a first portion of the first semiconductor is configured to function as a first channel formation region of the first transistor, and a first portion of the third conductor is configured to function as a second gate electrode of the first transistor,
wherein, in a second region corresponding to each intersecting portion of the plurality of second conductors and the structural body, the first insulator, one of the plurality of fourth conductors, the first semiconductor, the second insulator, the second semiconductor, and the third insulator are arranged concentrically in that order on the outside of the third conductor and the one of the plurality of fourth conductors is in contact with the first semiconductor,
wherein, in the second region, a first portion of one of the plurality of second conductors is configured to function as a first gate electrode of a second transistor, a first portion of the second semiconductor is configured to function as a second channel formation region of the second transistor, and a first portion of the one of the plurality of fourth conductors is configured to function as a second gate electrode of the second transistor,
wherein the first semiconductor comprises an oxide semiconductor,
wherein the second semiconductor comprises silicon,
wherein the second semiconductor comprises a region in contact with a first layer, and
wherein the first layer comprises a first metal element.
8 . A semiconductor device comprising:
a structural body extending in a first direction;
a plurality of first conductors extending in a second direction that intersects with the first direction; and
a plurality of second conductors extending in the second direction,
wherein the structural body comprises:
a third conductor;
a first insulator;
a plurality of fourth conductors;
a first semiconductor;
a second insulator;
a second semiconductor; and
a third insulator,
wherein, in a first region where the plurality of first conductors and the structural body intersect each other, the first insulator, the first semiconductor, the second insulator, the second semiconductor, and the third insulator are arranged concentrically around the third conductor in that order with the first insulator being in contact with the third conductor,
wherein, in the first region, a first portion of one of the plurality of first conductors is configured to function as a first gate electrode of a first transistor, a first portion of the first semiconductor is configured to function as a first channel formation region of the first transistor, and a first portion of the third conductor is configured to function as a second gate electrode of the first transistor,
wherein, in a second region where the plurality of second conductors and the structural body intersect each other, the first insulator, one of the plurality of fourth conductors, the first semiconductor, the second insulator, the second semiconductor, and the third insulator are arranged concentrically around the third conductor in that order and the one of the plurality of fourth conductors is in contact with the first semiconductor,
wherein, in the second region, a first portion of one of the plurality of second conductors is configured to function as a first gate electrode of a second transistor, a first portion of the second semiconductor is configured to function as a second channel formation region of the second transistor, and a first portion of the one of the plurality of fourth conductors is configured to function as a second gate electrode of the second transistor,
wherein the first semiconductor comprises an oxide semiconductor,
wherein the second semiconductor comprises silicon,
wherein the second semiconductor comprises a region in contact with a first layer, and
wherein the first layer comprises a first metal element.
9 . The semiconductor device according to claim 7 ,
wherein the first metal element is nickel,
wherein the first layer comprises an impurity element,
wherein the oxide semiconductor comprises at least one of indium and zinc, and
wherein the oxide semiconductor comprises CAAC-OS, nc-OS, or a-like OS.
10 . The semiconductor device according to claim 8 ,
wherein the first metal element is nickel,
wherein the first layer comprises an impurity element,
wherein the oxide semiconductor comprises at least one of indium and zinc, and
wherein the oxide semiconductor comprises CAAC-OS, nc-OS, or a-like OS.