IP Library › Granted Patent US 12,293,105
Granted Patent B2
US 12,293,105 · App. 18/343,929 · Granted May 6, 2025

Apparatuses and methods for memory alignment

Inventor: John D. Leidel (McKinney, TX)
G06F3/0647G06F3/061G06F3/0619G06F3/0683G06F12/10G11C7/1006G06F12/023G11C7/1012
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Quick Facts
Patent No.
US 12,293,105
App. No.
18/343,929
Granted
May 6, 2025
Kind
B2
Abstract

The present disclosure includes apparatuses and methods related to memory alignment. An example method comprises performing an alignment operation on a first byte-based memory element and a second byte-based memory element such that a padding bit of the first byte-based memory element is logically adjacent to a padding bit of the second byte-based memory element and a data bit of the first byte-based memory element is logically adjacent to a data bit of the second byte-based memory element.

Claims (72)

1. A method for memory alignment, comprising:

receiving, from a host, a logical address for data of a byte-based memory element of a memory allocation including a plurality of byte-based memory elements; and

translating the logical address to a physical address for the data based on:

a quantity of data bits of each of the plurality of byte-based memory elements;

a quantity of padding bits of each of the plurality of byte-based memory elements; and

a quantity of byte-based memory elements from a start of the memory allocation to the logical address,

wherein translating the logical address to the physical address comprises adjusting the logical address by a value equivalent to the quantity of padding bits multiplied by the quantity of byte-based memory elements from the start of the memory allocation to the logical address.

2. The method of claim 1 , further comprising defining the memory allocation at compile time,

wherein defining the memory allocation includes receiving a user-defined quantity of data bits in each of the byte-based memory elements of the memory allocation.

3. The method of claim 2 , wherein defining the memory allocation further includes receiving a user-defined length of the memory allocation.

4. The method of claim 1 , further comprising performing a logical operation on the data stored at the physical address.

5. An apparatus, comprising:

an array of memory cells configured to store a plurality of byte-based memory elements of a memory allocation; and

a controller coupled to the array of memory cells and configured to cause:

a logical address for data of a byte-based memory element of the memory allocation to be translated to a physical address for the data based on:

a quantity of data bits of each of the plurality of byte-based memory elements;

a quantity of padding bits of each of the plurality of byte-based memory elements; and

a quantity of byte-based memory elements from a start of the memory allocation to the logical address; and

the logical address to be adjusted by a value equivalent to the quantity of padding bits multiplied by the quantity of byte-based memory elements from the start of the memory allocation to the logical address.

6. The apparatus of claim 5 , wherein the controller is configured to receive a length of the memory allocation at compile time.

7. The apparatus of claim 6 , wherein the length of the memory allocation includes a user-defined quantity of data bits in each of the byte-based memory elements of the memory allocation.

8. The apparatus of claim 5 , wherein the controller is configured to receive a user-defined length of the memory allocation at compile time.

9. The apparatus of claim 5 , wherein the controller is configured to cause a logical operation to be performed on the data stored at the physical address.

10. A non-transitory machine-readable medium storing instructions executable by a processing resource to:

receive, from a host, a logical address for data of a byte-based memory element of a memory allocation stored on a memory device;

determine a physical address for the data based on:

a quantity of data bits of the byte-based memory element;

a quantity of padding bits of the byte-based memory element; and

a quantity of byte-based memory elements from a start of the memory allocation to the logical address;

store a plurality of byte-based memory elements of the memory allocation according to a byte-based alignment; and

store the plurality of byte-based memory elements of the memory allocation according to a non-byte-based alignment, wherein the byte-based memory element is a first byte-based memory element of the memory allocation, and wherein in the non-byte-based alignment at least one data bit of the first byte-based memory element and at least one data bit of a second byte-based memory element of the memory allocation are logically adjacent at a location of the memory allocation other than a byte boundary and stored in physically adjacent memory cells of the memory device.

11. The medium of claim 10 , further comprising instructions to perform an alignment operation on the first byte-based memory element and the second byte-based memory element from the byte-based alignment to the non-byte-based alignment.

12. The medium of claim 11 , further comprising instructions to perform a rotate operation on the at least one data bit of the first byte-based memory element and the at least one data bit of the second byte-based memory element to perform the alignment operation.

13. The medium of claim 12 , further comprising instructions to shift the at least one data bit of the second byte-based memory element by a quantity of bits equal to the quantity of padding bits of the byte-based memory element to perform the rotate operation.

14. The medium of claim 11 , further comprising instructions to perform a realignment operation to return the first byte-based memory element and the second byte-based memory element to the byte-based alignment.

15. A method for memory alignment, comprising:

receiving, from a host, a logical address for data of a byte-based memory element of a memory allocation including a plurality of byte-based memory elements;

translating the logical address to a physical address for the data based on:

a quantity of data bits of each of the plurality of byte-based memory elements;

a quantity of padding bits of each of the plurality of byte-based memory elements; and

a quantity of byte-based memory elements from a start of the memory allocation to the logical address;

performing a logical operation on the data at the physical address;

padding the data with the quantity of padding bits after performing the logical operation; and

sending the padded data to the host.

16. A method for memory alignment, comprising:

receiving, from a host, a logical address for data of a byte-based memory element of a memory allocation including a plurality of byte-based memory elements;

translating the logical address to a physical address for the data based on:

a quantity of data bits of each of the plurality of byte-based memory elements;

a quantity of padding bits of each of the plurality of byte-based memory elements; and

a quantity of byte-based memory elements from a start of the memory allocation to the logical address; and

storing, according to a non-byte-based alignment, logically adjacent bits in physically adjacent memory cells of a memory array, wherein the byte-based memory element is a first byte-based memory element of the memory allocation and the non-byte-based alignment includes:

at least one padding bit of the first byte-based memory element logically adjacent to at least one padding bit of a second byte-based memory element of the memory allocation; and

at least one data bit of the first byte-based memory element logically adjacent to at least one data bit of the second byte-based memory element at a location of the memory allocation other than a byte boundary.

17. The method of claim 16 , further comprising performing a logical operation on the data stored at the physical address.

18. An apparatus, comprising:

an array of memory cells configured to store a plurality of byte-based memory elements of a memory allocation;

a controller coupled to the array of memory cells and configured to cause a logical address for data of a byte-based memory element of the memory allocation to be translated to a physical address for the data based on:

a quantity of data bits of each of the plurality of byte-based memory elements;

a quantity of padding bits of each of the plurality of byte-based memory elements; and

a quantity of byte-based memory elements from a start of the memory allocation to the logical address;

wherein the controller is further configured to cause the data to be padded with the quantity of padding bits.

19. The apparatus of claim 18 , wherein the controller is further configured to cause a logical operation to be performed on the data at the physical address; and cause the data to be padded with the quantity of padding bits subsequent to performance of the logical operation.

20. A system, comprising:

a host; and

a memory device coupled to the host and configured to:

receive, from the host, a logical address for data of a byte-based memory element of a memory allocation stored on the memory device;

determine a physical address for the data based on:

a quantity of data bits of the byte-based memory element;

a quantity of padding bits of the byte-based memory element; and

a quantity of byte-based memory elements from a start of the memory allocation to the logical address;

perform a logical operation on the data stored at the determined physical address; and

subsequent to performing the logical operation, pad the data with the quantity of padding bits, wherein the host is configured to receive the padded data.

Assignments (2)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Nov 19, 2024
From: MICRON TECHNOLOGY, INC.
To: LODESTAR LICENSING GROUP LLC
Reel/Frame 069330/0015 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 29, 2023
From: LEIDEL, JOHN D.
To: MICRON TECHNOLOGY, INC.
Reel/Frame 064112/0693 →
Continuity (4)
Continuation 17360533 · Jun 28, 2021
Continuation 16574847 · Sep 18, 2019
Division 15349492 · Nov 11, 2016
Related Publication 20230418503A1 · Dec 28, 2023
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