Stacked ferroelectric structure
The present disclosure relates to an integrated circuit (IC) in which a memory structure comprises a ferroelectric structure without critical-thickness limitations. The memory structure comprises a first electrode and the ferroelectric structure. The ferroelectric structure is vertically stacked with the first electrode and comprises a first ferroelectric layer, a second ferroelectric layer, and a first restoration layer. The second ferroelectric layer overlies the first ferroelectric layer, and the first restoration layer is between and borders the first and second ferroelectric layers. The first restoration layer is a different material type than that of the first and second ferroelectric layers and is configured to decouple crystalline lattices of the first and second ferroelectric layers so the first and second ferroelectric layers do not reach critical thicknesses. A critical thickness corresponds to a thickness at and above which the orthorhombic phase becomes thermodynamically unstable, such that remanent polarization is lost.
1. A device, comprising:
a first conductive electrode;
a stack structure overlying the first conductive electrode; and
a second conductive electrode overlying the stack structure;
wherein the stack structure comprises a first metal oxide layer overlying the first conductive electrode, a first ferroelectric layer overlying the first metal oxide layer, and a second metal oxide layer overlying the first ferroelectric layer and underlying the second conductive electrode, wherein the first metal oxide layer, the first ferroelectric layer, and the second metal oxide layer have a common width, wherein the first and second metal oxide layers have a common material composition, which is different than a material composition of the first ferroelectric layer, and wherein the first and second metal oxide layers are ferroelectric.
2. The device according to claim 1 , wherein the device is a capacitor.
3. The device according to claim 1 , wherein the first metal oxide layer and the second metal oxide layer comprise zirconium oxide crystalized with a majority phase being orthorhombic.
4. The device according to claim 3 , wherein the first ferroelectric layer comprises hafnium oxide.
5. A device, comprising:
a first conductive electrode;
a first stack structure overlying the first conductive electrode;
a second stack structure overlying and spaced from the first stack structure;
a second conductive electrode overlying the second stack structure; and
a layer between and directly contacting the first stack structure and the second stack structure;
wherein the first stack structure entirely underlies the layer, wherein the second stack structure entirely overlies the layer, and wherein each of the first and second stack structures comprises a first metal oxide layer, a ferroelectric layer overlying the first metal oxide layer, and a second metal oxide layer overlying the ferroelectric layer.
6. The device according to claim 5 , wherein the layer comprises amorphous Indium-Gallium-Zinc-Oxide (a-IGZO), wherein the first and second metal oxide layers of the first and second stack structures comprise zirconium oxide, and wherein the ferroelectric layers of the first and second stack structures comprise hafnium oxide.
7. The device according to claim 5 , wherein the first metal oxide layer of the first stack structure, the ferroelectric layer of the first stack structure, and the second metal oxide layer of the first stack structure have a common width that is different than individual widths of the first and second conductive electrodes.
8. An integrated circuit comprising a device, wherein the device comprises:
a first conductive electrode;
a second conductive electrode overlying the first conductive electrode; and
a stack structure between the first conductive electrode and the second conductive electrode, wherein the stack structure comprises a first metal oxide layer, a first ferroelectric layer overlying the first metal oxide layer, a second metal oxide layer overlying the first ferroelectric layer, and a second ferroelectric layer overlying the second metal oxide layer and underlying the second conductive electrode, wherein the first and second ferroelectric layers have a same material composition different than a material composition of the first metal oxide layer and a material composition of the second metal oxide layer.
9. The device according to claim 1 , wherein the stack structure further comprises:
a second ferroelectric layer overlying the second metal oxide layer and having a material composition that is the same as the material composition of the first ferroelectric layer; and
a semiconductor channel layer overlying the second ferroelectric layer and having a material composition different than the material composition of the second ferroelectric layer, wherein the second conductive electrode overlies the semiconductor channel layer.
10. The device according to claim 9 , wherein the first metal oxide layer directly contacts the first conductive electrode, the first ferroelectric layer directly contacts the first metal oxide layer, the second metal oxide layer directly contacts the first ferroelectric layer, the second ferroelectric layer directly contacts the second metal oxide layer, the semiconductor channel layer directly contacts the second ferroelectric layer, and the second conductive electrode directly contacts the semiconductor channel layer.
11. The device according to claim 1 , wherein the material composition of the first ferroelectric layer has a critical thickness, which corresponds to a boundary between thermodynamic stability and thermodynamic instability as thickness of the material composition increases, wherein the first ferroelectric layer has a thickness less than the critical thickness, and wherein the stack structure has a thickness greater than the critical thickness.
12. The device according to claim 5 , wherein the layer is a semiconductor layer, wherein the first stack structure comprises a first blocking layer between and directly contacting the layer and the second metal oxide layer of the first stack structure, wherein the ferroelectric layer of the first stack structure and the layer have individual valence bands separated by a first offset, wherein the first blocking layer and the layer have individual valence bands separated by a second offset, wherein the second offset is greater than the first offset, and wherein the first blocking layer has a smaller valence band than the layer.
13. The device according to claim 12 , wherein the second stack structure comprises a second blocking layer between and directly contacting the layer and the first metal oxide layer of the second stack structure, and wherein the second blocking layer has a higher conduction band than the layer.
14. The device according to claim 5 , wherein the second metal oxide layer of the first stack structure directly contacts the ferroelectric layer of the first stack structure, which directly contacts the first metal oxide layer of the first stack structure, wherein the first and second metal oxide layers of the first stack structure and the first and second metal oxide layers of the second stack structure share a first material composition, wherein the ferroelectric layer of the first stack structure and the ferroelectric layer of the second stack structure share a second material composition, wherein the layer is a semiconductor layer and has a third material composition, and wherein the first, second, and third material compositions are different than each other.
15. The device according to claim 14 , wherein the first and second conductive electrodes are gate electrodes, and wherein the device further comprises:
a pair of source/drain contacts that are respectively on opposite sides of the second conductive electrode and that extend through an entire thickness of the second stack structure, from an elevation level with a top surface of the second conductive electrode to direct contact with the layer.
16. The integrated circuit according to claim 8 , further comprising:
a third conductive electrode level with the first conductive electrode; and
a semiconductor channel laterally between and directly contacting the first and third conductive electrodes and further underlying the first metal oxide layer, wherein the second conductive electrode corresponds to a gate electrode, and wherein the first and third conductive electrodes correspond to source/drain regions.
17. The integrated circuit according to claim 16 , wherein the first metal oxide layer directly contacts the semiconductor channel, the first ferroelectric layer directly contacts the first metal oxide layer, the second metal oxide layer directly contacts the first ferroelectric layer, the second ferroelectric layer directly contacts the second metal oxide layer, and the second conductive electrode directly contacts the second ferroelectric layer.
18. The integrated circuit according to claim 17 , wherein the semiconductor channel is amorphous Indium-Gallium-Zinc-Oxide (IGZO), wherein the first metal oxide layer is silicon-doped hafnium oxide, wherein the second metal oxide layer is zirconium oxide, and wherein the first and second ferroelectric layers are hafnium zirconium oxide.
19. The integrated circuit according to claim 8 , wherein the first metal oxide layer overlies and directly contacts the first conductive electrode, wherein the first ferroelectric layer directly contacts the first metal oxide layer, the second metal oxide layer directly contacts the first ferroelectric layer, and the second ferroelectric layer directly contacts the second metal oxide layer.
20. The integrated circuit according to claim 19 , wherein the first ferroelectric layer consists essentially of a first set of elements, wherein the second ferroelectric layer consists essentially of the first set of elements, wherein the first metal oxide layer consists essentially of a second set of elements, wherein the second metal oxide layer consists essentially of the second set of elements, wherein the second set of elements is different than the first set of elements, and wherein the first metal oxide layer is single crystalline, and wherein the second metal oxide layer is amorphous.