Apparatuses and methods for aggressor queue based mitigation threshold
Apparatuses and methods aggressor queue mitigation based threshold. A memory device detects aggressor rows by changing a count value associated with the row when it is accessed and comparing the count value to a mitigation threshold. Identified aggressor rows are stored in an aggressor queue. The value of the mitigation threshold is set based on a number of addresses which are stored in the aggressor queue. For example the threshold may increase as the number of addresses in the queue increases.
1 . An apparatus comprising:
an aggressor queue configured to store identified aggressor addresses;
a counter circuit configured to receive a row address and change a count value associated with the row address;
a threshold comparator circuit configured to compare the changed count value to a mitigation threshold and store the row address as an identified aggressor address in the aggressor queue; and
a mitigation threshold circuit configured to set a value of the mitigation threshold based on a number of the identified aggressor addresses stored in the aggressor queue.
2 . The apparatus of claim 1 , further comprising a memory array comprising a word line associated with a row address, wherein the count value is stored in memory cells along the word line.
3 . The apparatus of claim 1 , wherein the mitigation threshold circuit is configured to increase the mitigation threshold as the number of addresses in the aggressor queue increases.
4 . The apparatus of claim 1 , wherein the counter circuit is configured to increase the count value when the row address is received as part of an access operation.
5 . The apparatus of claim 1 , further comprising a refresh address generator configured to generate at least one refresh address based on a selected one of the identified aggressor addresses in the aggressor queue as part of a targeted refresh operation, wherein the selected one of the identified aggressor addresses is removed from the aggressor queue responsive to the targeted refresh operation.
6 . The apparatus of claim 1 , further comprising an alert logic circuit configured to issue an alert signal along an alert bus when the aggressor queue is full.
7 . The apparatus of claim 1 , further comprising a mode register configured to store a base threshold value and a threshold step value, wherein the mitigation threshold circuit is configured to set a value of the mitigation threshold based on the base threshold value plus the multiple of the threshold step value and a number of the identified aggressor addresses stored in the aggressor queue.
8 . An apparatus comprising:
a memory array comprising a plurality of word lines each associated with a row address and a count value;
an aggressor queue comprising a plurality of slots, wherein the aggressor queue is configured to provide a used slot signal which indicates a number of the plurality of slots which store an address;
an aggressor detection circuit configured to set a value of a mitigation threshold based on the used slot signal, and configured to determine if a row address is an aggressor address based on a comparison of the count value to the mitigation threshold when the row address is accessed and configured to store the aggressor row address in one of the plurality of slots.
9 . The apparatus of claim 8 , wherein the memory array comprises a plurality of counter memory cells along each of the plurality of word lines, wherein the plurality of counter memory cells are configured to store the count value associated with the word line.
10 . The apparatus of claim 8 , further comprising a refresh address generator configured to generate a refresh address based on a selected one of the stored addresses in the aggressor queue as part of a targeted refresh operation, wherein the selected one of the stored addresses is removed from the aggressor queue responsive to the targeted refresh operation.
11 . The apparatus of claim 8 , further comprising an aggressor detection circuit configured to change the count value in a first direction when the row is accessed and configured to reset the count value when the address is added to the queue.
12 . The apparatus of claim 8 , wherein the aggressor queue is configured to issue an queue full signal responsive to all of the plurality of slots being filled,
the apparatus further comprising an alert logic circuit configured to issue an alert signal responsive to the queue full signal.
13 . The apparatus of claim 8 , wherein the aggressor detection circuit is configured to increase the mitigation threshold as the used slot signal indicates a higher number of the plurality of slots are filled and configured to decrease the mitigation threshold as the used slot signal indicates a lower number of the plurality of slots are filled.
14 . A method comprising:
receiving an address, changing a count value associated with the address and comparing the count value to a threshold;
identifying the address as an aggressor address based on the comparing;
adding the aggressor address to an aggressor queue; and
changing a value of the threshold based on a number of aggressor addresses in the queue.
15 . The method of claim 14 , further comprising:
changing the value of the threshold in first direction responsive to increasing the number of aggressor addresses in the queue; and
changing the value of the threshold in a second direction opposite the first direction responsive to decreasing the number of aggressor addresses in the queue.
16 . The method of claim 14 , further comprising changing the value of the threshold by adding a base threshold size to a multiple of a threshold step size by the number of the aggressor addresses in the queue.
17 . The method of claim 14 , further comprising performing a targeted refresh operation on the aggressor address and removing the aggressor address from the aggressor queue responsive to the targeted refresh operation.
18 . The method of claim 14 , further comprising receiving the address as part of performing an access operation on a word line associated with the address.
19 . The method of claim 18 , wherein changing the count value includes reading the count value from memory cells along the word line, changing the count value, and writing the changed count value back to the memory cells.
20 . The method of claim 14 , further comprising activating an alert signal when the aggressor queue becomes full.