Method to produce 3D semiconductor devices and structures with memory
A method for producing a 3D semiconductor device including: providing a first level, the first level including a first single crystal layer; forming first alignment marks and control circuits in and/or on the first level, where the control circuits include first single crystal transistors and at least two interconnection metal layers; forming at least one second level disposed above the control circuits; performing a first etch step into the second level; forming at least one third level disposed on top of the second level; performing additional processing steps to form first memory cells within the second level and second memory cells within the third level, where each of the first memory cells include at least one second transistor, where each of the second memory cells include at least one third transistor, performing bonding of the first level to the second level, where the bonding includes oxide to oxide bonding.
1. A method for producing a 3D semiconductor device, the method comprising:
providing a first level, said first level comprising a first single crystal layer;
forming first alignment marks and control circuits in and/or on said first level,
wherein said control circuits comprise first single crystal transistors, and
wherein said control circuits comprise at least two interconnection metal layers;
forming at least one second level disposed above said control circuits;
performing a first etch step into said second level;
forming at least one third level disposed on top of said second level;
performing additional processing steps to form a plurality of first memory cells within said second level and a plurality of second memory cells within said third level,
wherein each of said plurality of first memory cells comprise at least one second transistor,
wherein each of said plurality of second memory cells comprise at least one third transistor; and
performing bonding of said first level to said second level,
wherein said bonding comprises oxide to oxide bonding.
2. The method according to claim 1 , further comprising:
processing said first memory cells into nonvolatile type memory cells.
3. The method according to claim 1 ,
wherein said second level comprises at least two overlaying layers.
4. The method according to claim 1 ,
wherein said etch step comprises reactive ion etching (“RIE”).
5. The method according to claim 1 ,
wherein said performing additional processing steps comprises using Atomic Layer Deposition (ALD).
6. The method according to claim 1 ,
wherein said at least one second transistor comprises a metal gate.
7. The method according to claim 1 ,
wherein said additional processing steps comprise depositing a gate electrode simultaneously for said second transistors and said third transistors.
8. A method for producing a 3D semiconductor device, the method comprising:
providing a first level, said first level comprising a first single crystal layer;
forming first alignment marks and control circuits in and/or on said first level,
wherein said control circuits comprise first single crystal transistors, and
wherein said control circuits comprise at least two interconnection metal layers;
forming at least one second level disposed above said control circuits;
performing a first etch step into said second level;
forming at least one third level disposed on top of said second level;
performing additional processing steps to form a plurality of first memory cells within said second level and a plurality of second memory cells within said third level,
wherein each of said plurality of first memory cells comprise at least one second transistor,
wherein each of said plurality of second memory cells comprise at least one third transistor,
wherein said additional processing steps comprise depositing a gate electrode simultaneously for said second transistors and said third transistors; and
performing bonding of said first level to said second level,
wherein said bonding comprises oxide to oxide bonding.
9. The method according to claim 8 ,
wherein said performing additional processing steps comprises using Atomic Layer Deposition (ALD).
10. The method according to claim 8 ,
wherein said second level comprises at least two overlaying layers.
11. The method according to claim 8 ,
wherein said gate electrode comprises tungsten.
12. The method according to claim 8 ,
wherein said etch step comprises reactive ion etching (“RIE”).
13. The method according to claim 8 ,
wherein said at least one second transistor comprises a metal gate.
14. The method according to claim 8 ,
wherein said memory comprises NAND type memory.
15. A method for producing a 3D semiconductor device, the method comprising:
providing a first level, said first level comprising a first single crystal layer;
forming first alignment marks and control circuits in and/or on said first level,
wherein said control circuits comprise first single crystal transistors, and
wherein said control circuits comprise at least two interconnection metal layers;
forming at least one second level disposed above said control circuits;
performing a first etch step into said second level;
forming at least one third level disposed on top of said second level;
performing additional processing steps to form a plurality of first memory cells within said second level and a plurality of second memory cells within said third level,
wherein each of said plurality of first memory cells comprise at least one second transistor,
wherein each of said plurality of second memory cells comprise at least one third transistor,
wherein said performing additional processing steps comprises using Atomic Layer Deposition (ALD); and
performing bonding of said first level to said second level,
wherein said bonding comprises oxide to oxide bonding.
16. The method according to claim 15 ,
wherein said additional processing steps comprise depositing a gate electrode simultaneously for said second transistors and said third transistors.
17. The method according to claim 15 ,
wherein said second level comprises at least two overlaying layers.
18. The method according to claim 15 ,
wherein said at least one second transistor comprises a metal gate.
19. The method according to claim 15 ,
wherein said memory comprises NAND type memory.
20. The method according to claim 15 ,
wherein said etch step comprises reactive ion etching (“RIE”).