Method for producing 3D semiconductor devices and structures with transistors and memory cells
A method for producing a 3D semiconductor device including: providing a first level, including a single crystal layer; forming memory control circuits in and/or on the first level which include first single crystal transistors and at least two interconnection metal layers; forming at least one second level; performing a first etch step into the second level; forming at least one third level on top of the second level; performing additional processing steps to form first memory cells within the second level and second memory cells within the third level, where each of the first memory cells include at least one second transistor including a metal gate, where each of the second memory cells include at least one third transistor; and performing bonding of the first level to the second level, where the first level includes control of power delivery to the at least one third transistor.
1 . A method for producing a 3D semiconductor device, the method comprising:
providing a first level, said first level comprising a first single crystal layer;
forming memory control circuits in and/or on said first level,
wherein said memory control circuits comprise first single crystal transistors, and
wherein said memory control circuits comprise at least two interconnection metal layers;
forming at least one second level;
performing a first etch step into said at least one second level;
forming at least one third level;
performing additional processing steps to form a plurality of first memory cells within said second level and a plurality of second memory cells within said third level,
wherein each of said plurality of first memory cells comprise at least one second transistor,
wherein each of said plurality of second memory cells comprise at least one third transistor, and
wherein said at least one second transistor comprises a metal gate; and
performing bonding of said first level to said second level,
wherein said third level is disposed above said second level, and
wherein said first level comprises control of power delivery to said at least one third transistor.
2 . The method according to claim 1 , further comprising:
processing said first memory cells into nonvolatile type memory cells.
3 . The method according to claim 1 ,
wherein said second level comprises at least two overlaying layers.
4 . The method according to claim 1 ,
wherein said first etch step comprises reactive ion etching (“RIE”).
5 . The method according to claim 1 ,
wherein said performing additional processing steps comprises use of Atomic Layer Deposition (ALD).
6 . The method according to claim 1 ,
wherein said metal gate comprises tungsten.
7 . The method according to claim 1 ,
wherein said bonding comprises oxide to oxide bonding.
8 . A method for producing a 3D semiconductor device, the method comprising:
providing a first level, said first level comprising a first single crystal layer;
forming memory control circuits in and/or on said first level,
wherein said memory control circuits comprise first single crystal transistors, and
wherein said memory control circuits comprise at least two interconnection metal layers;
forming at least one second level disposed above or below said memory control circuits;
performing a first etch step into said at least one second level;
forming at least one third level disposed on top of said second level; and
performing additional processing steps to form a plurality of first memory cells within said second level and a plurality of second memory cells within said third level,
wherein each of said plurality of first memory cells comprise at least one second transistor,
wherein each of said plurality of second memory cells comprise at least one third transistor,
wherein said additional processing steps comprise depositing a gate electrode simultaneously for said second transistors and said third transistors,
wherein said gate electrode comprises tungsten,
wherein said step of forming memory control circuits comprises an annealing step for dopant activation, and
wherein said annealing is reduced to accommodate the upcoming annealing steps for said second level and third level.
9 . The method according to claim 8 ,
wherein said performing additional processing steps comprises use of Atomic Layer Deposition (ALD).
10 . The method according to claim 8 ,
wherein said second level comprises at least two overlaying layers.
11 . The method according to claim 8 , further comprising:
a step of performing bonding of said first level to said second level.
12 . The method according to claim 8 ,
wherein said first etch step comprises reactive ion etching (“RIE”).
13 . The method according to claim 8 ,
wherein said first level comprises control of power delivery to said at least one third transistor.
14 . The method according to claim 8 ,
wherein said memory cells comprise a NAND type memory.
15 . A method for producing a 3D semiconductor device, the method comprising:
providing a first level, said first level comprising a first single crystal layer;
forming memory control circuits in and/or on said first level,
wherein said memory control circuits comprise first single crystal transistors, and
wherein said memory control circuits comprise at least two interconnection metal layers;
forming at least one second level disposed above or below said memory control circuits;
performing a first etch step into said at least one second level;
forming at least one third level disposed on top of said second level;
performing additional processing steps to form a plurality of first memory cells within said second level and a plurality of second memory cells within said third level,
wherein each of said plurality of first memory cells comprise at least one second transistor,
wherein each of said plurality of second memory cells comprise at least one third transistor;
forming at least one via, said at least one via is disposed through said third level and through said second level, and connects to at least one of said at least two interconnection metal layers; and
a step of gate replacement of said at least one third transistor.
16 . The method according to claim 15 ,
wherein said additional processing steps comprise depositing a gate electrode simultaneously for said second transistors and said third transistors.
17 . The method according to claim 15 ,
wherein said second level comprises at least two overlaying layers.
18 . The method according to claim 15 ,
wherein said at least one second transistor comprises a metal gate.
19 . The method according to claim 15 ,
wherein said memory cells comprise a NAND type memory.
20 . The method according to claim 15 , further comprising:
performing bonding of said first level to said second level,
wherein said bonding comprises oxide to oxide bonding.