Electronic device having a substrate-to-substrate interconnection structure and manufacturing method thereof
An electronic device and a method of making an electronic device. As non-limiting examples, various aspects of this disclosure provide various methods of manufacturing electronic devices, and electronic devices manufactured thereby, that comprise utilizing an adhesive layer to attach an upper electronic package to a lower die and/or utilizing metal pillars for electrically connecting the upper electronic package to a lower substrate, wherein the metal pillars have a smaller height above the lower substrate than the lower die.
1. An electronic device comprising:
a substrate comprising a top substrate side, a bottom substrate side, and lateral substrate sides between the top and bottom substrate sides;
a semiconductor die comprising a top die side, a bottom die side, and lateral die sides between the top and bottom die sides, wherein the bottom die side is coupled to the top substrate side;
a first conductive interconnection structure between the semiconductor die and the substrate and electrically connecting the semiconductor die to the substrate;
an upper semiconductor package comprising an upper substrate having a top upper substrate side, a bottom upper substrate side, and lateral upper substrate sides extending from the top upper substrate side to the bottom upper substrate side;
a substrate-to-substrate (S2S) interconnection structure that extends between the top substrate side and the bottom upper substrate side, wherein:
the S2S interconnection structure comprises a solder portion and a non-solder metal portion;
a first end of the non-solder metal portion is coupled to the solder portion and a second end of the non-solder metal portion is coupled to the top substrate side via a solderless bond; and
at least part of the non-solder metal portion of the S2S interconnection structure is positioned lateral of the semiconductor die between the top die side and the bottom die side; and
a first encapsulating material that covers at least the top substrate side.
2. The electronic device of claim 1 , wherein the first encapsulating material covers the lateral upper substrate sides.
3. The electronic device of claim 1 , comprising an underfill material that contacts the top substrate side, the bottom die side, and the lateral die sides, and where the first encapsulating material laterally surrounds the underfill material.
4. The electronic device of claim 1 , wherein the non-solder metal portion of the S2S interconnection structure comprises copper.
5. The electronic device of claim 4 , wherein the non-solder metal portion of the S2S interconnection structure comprises a copper post.
6. The electronic device of claim 1 , wherein in a vertical cross-section, the non-solder metal portion of the S2S interconnection structure is solid with no voids.
7. The electronic device of claim 1 , wherein the solder portion of the S2S interconnection structure is positioned vertically between the bottom upper substrate side and an uppermost surface of the non-solder metal portion of the S2S interconnection structure.
8. The electronic device of claim 1 , comprising a pad on the top substrate side, wherein the non-solder metal portion of the S2S interconnection structure is connected to the pad via the solderless bond.
9. The electronic device of claim 1 , wherein at least part of the solder portion of the S2S interconnection structure is positioned lateral of the semiconductor die between the top die side and the bottom die side.
10. The electronic device of claim 1 , wherein the first encapsulating material covers at least a portion of one or more of:
the bottom upper substrate side,
the lateral die sides, or
a lateral side of the S2S interconnection structure.
11. An electronic device comprising:
a lower substrate (LS) comprising a top LS side, a bottom LS side, and a lateral LS side between the top LS side and the bottom LS side, wherein the top LS side comprises a pad;
a semiconductor die comprising a top die side, a bottom die side coupled to the top LS side, and a lateral die side between the top die side and the bottom die side;
a first conductive interconnection structure between the semiconductor die and the lower substrate and electrically connecting the semiconductor die to the lower substrate;
an upper substrate (US) comprising a top US side, a bottom US side, and a lateral US side extending from the top US side to the bottom US side;
a substrate-to-substrate (S2S) interconnection structure that extends between the top LS side and the bottom US side, wherein the S2S interconnection structure comprises a solder portion and a non-solder metal portion, and wherein the non-solder metal portion comprises a copper post solderlessly connected to the pad; and
a first encapsulating material that covers at least the top LS side.
12. The electronic device of claim 11 , wherein the first encapsulating material covers the lateral US side.
13. The electronic device of claim 11 , wherein a first end of the non-solder metal portion is coupled to the solder portion and a second end of the non-solder metal portion is coupled to the pad on the top LS side via a solderless bond.
14. The electronic device of claim 11 , wherein in a vertical cross section, the non-solder metal portion of the S2S interconnection structure is solid with no voids.
15. The electronic device of claim 11 , wherein the solder portion of the S2S interconnection structure is positioned vertically between the bottom US side and an uppermost surface of the non-solder metal portion of the S2S interconnection structure.
16. The electronic device of claim 11 , wherein at least part of the non-solder metal portion of the S2S interconnection structure is positioned lateral of the semiconductor die between the top die side and the bottom die side.
17. The electronic device of claim 11 , wherein at least part of the solder portion of the S2S interconnection structure is positioned lateral of the semiconductor die between the top die side and the bottom die side.
18. The electronic device of claim 11 , comprising an underfill material that contacts the top LS side, the bottom die side, and the lateral die side, and where the first encapsulating material laterally surrounds the underfill material.
19. The electronic device of claim 11 , wherein the first encapsulating material covers at least a portion of one or more of:
the bottom US side,
the lateral die side, or
a lateral side of the S2S interconnection structure.
20. A method of manufacturing an electronic device, the method comprising:
providing a substrate comprising a top substrate side, a bottom substrate side, and lateral substrate sides between the top and bottom substrate sides;
providing a semiconductor die comprising a top die side, a bottom die side, and lateral die sides between the top and bottom die sides, wherein the bottom die side is coupled to the top substrate side;
providing a first conductive interconnection structure between the semiconductor die and the substrate and electrically connecting the semiconductor die to the substrate;
providing an upper semiconductor package comprising an upper substrate having a top upper substrate side, a bottom upper substrate side, and lateral upper substrate sides extending from the top upper substrate side to the bottom upper substrate side;
providing a substrate-to-substrate (S2S) interconnection structure that extends between the top substrate side and the bottom upper substrate side, wherein:
the S2S interconnection structure comprises a solder portion and a non-solder metal portion;
a first end of the non-solder metal portion is coupled to the solder portion and a second end of the non-solder metal portion is coupled to the top substrate side via a solderless bond; and
at least part of the non-solder metal portion of the S2S interconnection structure is positioned lateral of the semiconductor die between the top die side and the bottom die side; and
providing a first encapsulating material that covers at least the top substrate side.