Method for forming memory device with buried gate in peripheral circuit region
View Patent ↗A method for forming a semiconductor structure for a memory device, including providing a substrate comprising a memory cell region and a peripheral circuit region defined thereon, and the peripheral circuit region comprising at least an active region formed therein, forming at least a buried gate structure in the active region, and an insulating layer being formed on a top of the buried gate structure, and forming a conductive line structure on the buried gate structure, and the conductive line structure and the buried gate structure being physically spaced apart and electrically isolated from each other by the insulating layer.
1. A method for forming a semiconductor structure for a memory device, comprising:
providing a substrate comprising a memory cell region and a peripheral circuit region defined thereon, and the peripheral circuit region comprising at least an active region formed therein;
forming at least a buried gate structure in the active region, and an insulating layer being formed on a top of the buried gate structure;
forming a conductive line structure on the buried gate structure, and the conductive line structure and the buried gate structure being physically spaced apart and electrically isolated from each other by the insulating layer;
after forming the conductive line structure, forming a local inter connection structure, wherein the local inter connection structure electrically connects the conductive line structure and the active region at a first side of the buried gate structure; and
forming an interconnection structure, wherein the interconnection structure is formed at a second side of the buried gate structure opposite to the first side, and the interconnection structure electrically connects the active region to a bit line, or alternatively electrically connecting the active region to a bit line bar.
2. The method for forming the semiconductor structure for the memory device according to claim 1 , wherein the local inter connection structure comprises:
at least a first contact plug formed on the conductive line structure;
at least a second contact plug formed in the active region on the first side of the buried gate structure; and
at least a connecting layer electrically connecting the first contact plug and the second contact plug.
3. The method for forming the semiconductor structure for the memory device according to claim 2 , wherein the second contact plug comprises a contact plug upper portion and a contact plug lower portion, the contact plug upper portion and the first contact plug comprise a same material, and the contact plug lower portion and the conductive line structure comprise a same material.
4. The method for forming the semiconductor structure for the memory device according to claim 1 , wherein the peripheral circuit region further comprises multiple of the active regions formed therein, the conductive line structure is right above the buried gate structure and completely overlaps the buried gate structure, a longitudinal axis of the conductive line structure and a longitudinal axis of the buried gate structure extend in a same horizontal direction parallel to a surface of the substrate across the active regions.