MRAM stacks, MRAM devices and methods of forming the same
Memory stacks, memory devices and method of forming the same are provided. A memory stack includes a spin-orbit torque layer, a magnetic bias layer and a free layer. The magnetic bias layer is in physical contact with the spin-orbit torque layer and has a first magnetic anisotropy. The free layer is disposed adjacent to the spin-orbit torque layer and has a second magnetic anisotropy perpendicular to the first magnetic anisotropy.
1. A memory stack, comprising:
a heavy metal layer;
a synthetic free layer disposed over the heavy metal layer and comprising:
a first free layer with a first magnetic anisotropy perpendicular to a upper surface of the heavy metal layer;
a second free layer with a second magnetic anisotropy parallel to the upper surface of the heavy metal layer; and
a non-magnetic metal spacer disposed between and in direct contact with the first free layer and the second free layer;
a reference layer disposed over the synthetic free layer; and
a synthetic anti-ferromagnetic layer disposed over the reference layer and configured to fix a magnetic anisotropy of the reference layer.
2. The memory stack of claim 1 , wherein the first free layer is in direct contact with the heavy metal layer.
3. The memory stack of claim 1 , wherein the first free layer comprises Co, CoNi or a combination thereof.
4. The memory stack of claim 1 , wherein the second free layer comprises Fe, Co, Ni, FeCo, CoNi, CoFeB, FeB, FePt, FePd or a combination thereof.
5. The memory stack of claim 1 , wherein the non-magnetic metal spacer comprises PtCo, WCoFeB, Ru, RuFe, RuCo, Ir, IrFe, IrCo or a combination thereof.
6. The memory stack of claim 1 , further comprising:
a tunneling barrier layer disposed between the reference layer and the synthetic free layer.
7. A memory device, comprising:
a substrate; and
a MRAM cell disposed over the substrate and comprising:
a bottom electrode;
a heavy metal layer disposed over the bottom electrode;
a synthetic free layer disposed over the heavy metal layer and comprising two layers configured to have magnetic anisotropies perpendicular to each other;
a reference layer disposed over the synthetic free layer; and
a synthetic anti-ferromagnetic layer disposed over the reference layer and configured to fix a magnetic anisotropy of the reference layer;
a top electrode disposed over the synthetic anti-ferromagnetic layer, wherein a sidewall of the top electrode is flush with a sidewall of the synthetic free layer.
8. The memory device of claim 7 , wherein the layer of the synthetic free layer that is in physical contact with the heavy metal layer forms a perpendicular magnetic anisotropy with the heavy metal layer.
9. The memory device of claim 7 , further comprising:
a tunneling barrier layer disposed between the reference layer and the synthetic free layer.
10. A memory stack, comprising:
a metal layer;
a synthetic free layer disposed over the metal layer and comprising:
a first free layer with a first magnetic anisotropy perpendicular to a upper surface of the metal layer; and
a second free layer with a second magnetic anisotropy parallel to the upper surface of the metal layer;
a reference layer disposed over the synthetic free layer; and
a synthetic anti-ferromagnetic layer, disposed over the reference layer and configured to fix a magnetic anisotropy of the reference layer,
wherein a width of the metal layer is different from a width of the synthetic free layer.
11. The memory stack of claim 10 , wherein the width of the metal layer is greater than the width of the synthetic free layer.
12. The memory stack of claim 10 , wherein the first free layer is in direct contact with the metal layer.
13. The memory stack of claim 10 , wherein the first free layer and the second free layer are separated from each other.
14. The memory stack of claim 10 , wherein the synthetic anti-ferromagnetic layer comprises at least one non-magnetic metal layer and at least one pinned ferromagnetic layer adjacent to each other.
15. The memory stack of claim 10 , further comprising:
a tunneling barrier layer disposed between the reference layer and the synthetic free layer.
16. The memory stack of claim 10 , wherein the metal layer comprises W, Pt, AuPt or a combination thereof.
17. The memory stack of claim 10 , wherein the first free layer comprises Co, CoNi or a combination thereof.
18. The memory stack of claim 10 , wherein the second free layer comprises FeCo, CoFeB, FeB or a combination thereof.
19. The memory stack of claim 10 , further comprising a capping structure disposed over the synthetic anti-ferromagnetic layer.
20. The memory stack of claim 19 , wherein the capping structure comprises a first capping layer and an overlaying second capping layer, and the first capping layer and the second capping layer comprise different metal materials.