Redistribution structure for semiconductor device and method of forming same
View Patent ↗A semiconductor device having a redistribution structure and a method of forming the same are provided. A semiconductor device includes a semiconductor structure, a redistribution structure over and electrically coupled the semiconductor structure, and a connector over and electrically coupled to the redistribution structure. The redistribution structure includes a base via and stacked vias electrically interposed between the base via and the connector. The stacked vias are laterally spaced apart from the base via.
1. A method comprising:
forming a redistribution structure over a semiconductor structure, wherein the semiconductor structure comprises a first connector, wherein forming the redistribution structure comprises:
forming a first insulating layer directly on the semiconductor structure;
forming a first metallization pattern, the first metallization pattern comprising a base via and a first redistribution line, the base via extending through the first insulating layer over the first connector of the semiconductor structure; and
forming stacked vias over the first insulating layer, the stacked vias being electrically coupled to the base via, wherein a first via of the stacked vias physically contacts the first redistribution line, the stacked vias overlapping each other; and
forming a second connector over the redistribution structure, wherein the stacked vias electrically couple the first connector to the second connector, wherein the stacked vias are laterally between the first connector and the second connector in a cross-sectional view.
2. The method of claim 1 , wherein the stacked vias are completely non-overlapping the base via.
3. The method of claim 1 , wherein the stacked vias are completely non-overlapping the first connector and the second connector in the cross-sectional view.
4. The method of claim 1 , wherein forming the redistribution structure further comprises:
forming a dummy line, the dummy line being adjacent a first conductive line between a first stacked via and a second stacked via of the stacked vias, wherein the first stacked via and the second stacked via are adjacent vias of the stacked vias.
5. The method of claim 4 , wherein forming the redistribution structure further comprises:
forming a second conductive line between a third stacked via and a fourth stacked via of the stacked vias, wherein the second conductive line overlaps the dummy line.
6. The method of claim 1 , wherein the base via has a first width at a first distance from the semiconductor structure and a second width at a second distance from the semiconductor structure, the first width being less than the second width, the first distance being less than the second distance.
7. The method of claim 1 , wherein a width of the base via is less than a width of the first connector.
8. A method comprising:
forming a redistribution structure over a semiconductor structure, wherein the semiconductor structure comprises a first connector, wherein forming the redistribution structure comprises:
forming a first insulating layer directly on the semiconductor structure;
forming a first metallization pattern, the first metallization pattern comprising a base via and a first redistribution line, the base via extending through the first insulating layer over the first connector of the semiconductor structure; and
forming stacked vias over the first insulating layer, the stacked vias being electrically coupled to the base via, wherein the stacked vias overlap each other, wherein a first via of the stacked vias physically contacts the first redistribution line; and
forming a second connector over the redistribution structure, wherein the stacked vias electrically couple the first connector to the second connector, wherein the stacked vias are laterally spaced apart from the first connector and the second connector in a cross-sectional view.
9. The method of claim 8 , wherein the stacked vias are completely non-overlapping the base via.
10. The method of claim 9 , wherein the stacked vias are completely non-overlapping the first connector.
11. The method of claim 8 , wherein the stacked vias are completely non-overlapping the first connector and the second connector in the cross-sectional view.
12. The method of claim 8 , wherein the stacked vias are laterally between the first connector and the base via.
13. The method of claim 8 , wherein the second connector is laterally between the stacked vias and the base via.
14. The method of claim 8 , wherein the second connector overlaps the base via.
15. A semiconductor device comprising:
a redistribution structure over a semiconductor structure, wherein the semiconductor structure comprises a first connector, wherein the redistribution structure comprises:
a first insulating layer directly on the semiconductor structure;
a first metallization pattern, the first metallization pattern comprising a base via and a first redistribution line, the base via extending through the first insulating layer to physically contact the first connector; and
stacked vias over the first insulating layer, the stacked vias being electrically coupled to the base via, wherein a first via of the stacked vias physically contacts the first redistribution line, the stacked vias overlapping each other; and
a second connector over the redistribution structure, wherein the stacked vias electrically couple the first connector to the second connector, wherein the stacked vias are completely spaced apart from the first connector and the second connector in a cross-sectional view.
16. The semiconductor device of claim 15 , wherein the stacked vias are laterally between the first connector and the second connector.
17. The semiconductor device of claim 15 , wherein the second connector is laterally between the stacked vias and the first connector via in the cross-sectional view.
18. The semiconductor device of claim 15 , further comprising a dummy line, wherein the dummy line overlaps the base via.
19. The semiconductor device of claim 15 , wherein the redistribution structure further comprises a second redistribution line between a first stacked via and a second stacked via of the stacked vias, wherein the second redistribution line electrically couples the first stacked via to the second stacked via of the stacked vias, wherein the second redistribution line overlaps the base via.
20. The semiconductor device of claim 15 , wherein the second connector overlaps the first connector.