Semiconductor devices
A semiconductor device may include first and second channel patterns on a substrate, first and second source/drain patterns in contact respectively with the first and second channel patterns, and first and second gate electrodes respectively overlapping the first and second channel patterns. The first gate electrode may include a first segment between first and second semiconductor patterns of the first channel pattern. The first segment may include a first convex portion protruding toward the first source/drain pattern. The second gate electrode may include a second segment between third and fourth semiconductor patterns of the second channel pattern. The second segment may include a concave portion recessed toward a center of the second segment.
1. A method of manufacturing a semiconductor device, comprising:
forming a first preliminary pattern on a substrate, the first preliminary pattern including first sacrificial layers and first semiconductor layers that are alternately and repeatedly stacked on the substrate;
forming a first sacrificial pattern on the first preliminary pattern, the first sacrificial pattern extending in a first direction;
forming a first recession by etching the first preliminary pattern using the first sacrificial pattern as an etching mask;
forming a first source/drain pattern in the first recession;
exposing the first sacrificial layers by selectively removing the first sacrificial pattern;
performing a first etching process to selectively remove the first sacrificial layers, thereby forming first cavities of different widths;
forming side recessions on a side surface of the first source/drain pattern, the side recessions being adjacent to corresponding the first cavities of different widths; and
forming a first gate electrode on the first semiconductor layers, the first gate electrode including first segments in corresponding the first cavities of different widths;
wherein each of the first segments includes a convex portion that protrudes toward a corresponding one of the side recessions and the corresponding one of the side recessions has a concavely curved shape.
2. The method of claim 1 , wherein a lowermost one of the first cavities of different widths has a first width in a second direction,
wherein an uppermost one of the first cavities of different widths has a second width in the second direction, and
wherein the first width is greater than the second width.
3. The method of claim 1 , wherein the side recessions are formed together when the first cavities are formed.
4. The method of claim 1 , further comprising:
forming a second preliminary pattern on the substrate, the second preliminary pattern including second sacrificial layers and second semiconductor layers that are alternately and repeatedly stacked on the substrate;
forming a second sacrificial pattern on the second preliminary pattern, the second sacrificial pattern extending in the first direction;
forming a second recession by etching the second preliminary pattern using the second sacrificial pattern as an etching mask;
forming barrier insulation patterns on corresponding the second sacrificial layers that are exposed by the second recession;
forming a second source/drain pattern in the second recession;
exposing the second sacrificial layers by selectively removing the second sacrificial pattern;
performing a second etching process to selectively remove the second sacrificial layers, thereby forming second cavities; and
forming a second gate electrode on the second semiconductor layers, the second gate electrode including second segments in corresponding the second cavities.
5. The method of claim 4 , wherein each of the barrier insulation patterns protrudes toward a corresponding one of the second segments.
6. The method of claim 4 , wherein each of the second segments includes a concave portion facing a corresponding one of the barrier insulation patterns.
7. The method of claim 4 , wherein a lowermost one of the second cavities has a third width in a second direction,
wherein an uppermost one of the second cavities has a fourth width in the second direction, and
wherein the third width is greater than the fourth width.
8. The method of claim 7 , wherein a lowermost one of the first cavities has a first width in the second direction,
wherein the first width is greater than the third width.
9. A method of manufacturing a semiconductor device, comprising:
forming an active pattern on a substrate, the active pattern including sacrificial layers and semiconductor layers that are alternately and repeatedly stacked on the substrate;
forming a source/drain pattern on a side surface of the active pattern;
selectively removing the sacrificial layers to form cavities of different widths;
forming side recessions on a side surface of the source/drain pattern, the side recessions being adjacent to corresponding the cavities of different widths; and
forming a gate electrode on the semiconductor layers, the gate electrode including segments in corresponding the cavities of different widths,
wherein each of the cavities of different widths protruding toward a corresponding one of the side recessions; and
wherein each of the segments includes a convex portion protruding toward the corresponding one of the side recessions and the corresponding one of the side recessions has a concavely curved shape.
10. The method of claim 9 , wherein forming the side recessions includes partially etching the side surface of the source/drain pattern through corresponding the cavities.
11. The method of claim 9 , wherein the cavities of different widths include a first cavity and a second cavity on the first cavity,
wherein the first cavity has a first width,
wherein the second cavity has a second width, and
wherein the first width is greater than the second width.
12. A method of manufacturing a semiconductor device, comprising:
forming an active pattern on a substrate, the active pattern including sacrificial layers and semiconductor layers that are alternately and repeatedly stacked on the substrate;
partially etching sides of the sacrificial layers to form depressions adjacent to corresponding the sacrificial layers;
forming barrier insulation patterns in corresponding the depressions;
forming a source/drain pattern on a side surface of the active pattern;
selectively removing the sacrificial layers to form cavities of different widths; and
forming a gate electrode on the semiconductor layers, the gate electrode including segments in corresponding the cavities of different widths,
wherein each of the barrier insulation patterns protruding toward a corresponding one of the cavities of different widths;
wherein each of the segments includes a concave portion,
wherein each of the barrier insulation patterns includes a convex portion, and
wherein the concave portion faces the convex portion.
13. The method of claim 12 , wherein the barrier insulation patterns are configured to protect the source/drain pattern when the sacrificial layers are removed.
14. The method of claim 12 , wherein forming the barrier insulation patterns includes:
forming a barrier insulation layer that conforms to and fills the depressions; and
performing an isotropic etching process to partially etch the barrier insulation layer.
15. The method of claim 12 , wherein the cavities of different widths include a first cavity and a second cavity on the first cavity, wherein the first cavity has a first width, wherein the second cavity has a second width, and wherein the first width is greater than the second width.