3T memory with enhanced speed of operation and data retention
A memory device including a plurality of memory cells, at least one of the plurality of memory cells includes a first transistor, a second transistor, and a third transistor. The first transistor includes a first drain/source path and a first gate structure electrically coupled to a write word line. The second transistor includes a second drain/source path and a second gate structure electrically coupled to the first drain/source path of the first transistor. The third transistor includes a third drain/source path electrically coupled to the second drain/source path of the second transistor and a third gate structure electrically coupled to a read word line. Where, the first transistor, and/or the second transistor, and/or the third transistor is a ferroelectric field effect transistor or a negative capacitance field effect transistor.
1. A memory device, comprising:
a plurality of memory cells, at least one memory cell of the plurality of memory cells including three transistors that form a storage node that stores a bit of data of the at least one memory cell, the three transistors including:
a first transistor of the transistors including a first drain/source path and including a first gate structure connected to a write word line;
a second transistor of the three transistors including a second drain/source path and including a second gate structure connected to the first drain/source path of the first transistor at the storage node of the at least one memory cell; and
a third transistor of the three transistors including a third drain/source path connected to the second drain/source path of the second transistor and including a third gate structure connected to a read word line without being connected to the second gate structure or the storage node of the at least one memory cell,
wherein the first transistor, and/or the second transistor, and/or the third transistor is a ferroelectric field effect transistor or a negative capacitance field effect transistor.
2. The memory device of claim 1 , wherein the first transistor is a ferroelectric field effect transistor.
3. The memory device of claim 1 , wherein the second transistor is a negative capacitance field effect transistor.
4. The memory device of claim 1 , wherein the third transistor is a ferroelectric field effect transistor.
5. The memory device of claim 1 , wherein the first transistor is a negative capacitance field effect transistor.
6. The memory device of claim 1 , wherein the second transistor is a ferroelectric field effect transistor.
7. The memory device of claim 1 , wherein the third transistor is a negative capacitance field effect transistor.
8. The memory device of claim 1 , wherein the first transistor is a ferroelectric field effect transistor, and the second transistor is a negative capacitance field effect transistor.
9. The memory device of claim 1 , wherein the first transistor is a negative capacitance field effect transistor, and the second transistor is a ferroelectric field effect transistor.
10. The memory device of claim 1 , wherein the third gate structure of the third transistor includes a high k dielectric.
11. The memory device of claim 1 , wherein the ferroelectric field effect transistor and/or the negative capacitance field effect transistor includes hafnium zirconium oxide (HZO).
12. A memory device, comprising:
a plurality of memory cells, at least one memory cell of the plurality of memory cells including three transistors that form a storage node that stores a bit of data of the at least one memory cell, the three transistors including:
a first negative capacitance field effect transistor of the three transistors including a first drain/source path and including a first gate structure that is connected to a write word line;
a ferroelectric field effect transistor of the three transistors including a second drain/source path and including a second gate structure that is connected to the first drain/source path of the first negative capacitance field effect transistor at the storage node of the at least one memory cell, and
a second negative capacitance field effect transistor of the three transistors including a third drain/source path connected to the second drain/source path of the ferroelectric field effect transistor and including a third gate structure connected to a read word line without being connected to the second gate structure of the storage node at least one memory cell.
13. The memory device of claim 12 , wherein the first gate structure, and/or the second gate structure, and/or the third gate structure includes hafnium zirconium oxide (HZO).
14. The memory device of claim 12 , comprising a first fin structure in a first direction, wherein the second gate structure and the third gate structure are spaced apart and situated across the first fin structure in a second direction that is non-parallel with the first direction.
15. The memory device of claim 14 , comprising a second fin structure in the first direction and spaced apart from the first fin structure, wherein the first gate structure is situated across the second fin structure in the second direction.
16. A memory device, comprising:
a plurality of memory cells, at least one memory cell of the plurality of memory cells including three transistors that form a storage node that stores a bit of data of the at least one memory cell, the three transistors including:
a first transistor of the three transistors including a first drain/source path connected at one end to a write bit line and including a first gate structure connected to a write word line;
a second transistor of the three transistors including a second drain/source path connected at one end to receive a power supply voltage and including a second gate structure connected to another end of the first drain/source path of the first transistor at the storage node of the at least one memory cell; and
a third transistor of the three transistors including a third drain/source path connected at one end to a read bit line and at another end to the second drain/source path of the second transistor and including a third gate structure connected to a read word line without being directly connected to the second gate structure or the storage node of the at least one memory cell,
wherein the first transistor, and/or the second transistor, and/or the third transistor is a ferroelectric field effect transistor or a negative capacitance field effect transistor.
17. The memory device of claim 16 , wherein the first transistor is a ferroelectric field effect transistor.
18. The memory device of claim 16 , wherein the second transistor is a negative capacitance field effect transistor.
19. The memory device of claim 16 , wherein the third transistor is a ferroelectric field effect transistor.
20. The memory device of claim 16 , wherein the first transistor is a negative capacitance field effect transistor, and the second transistor is a ferroelectric field effect transistor.