Granted Patent B2

US 12,426,250 · App. 17/948,872 · Granted Sep 23, 2025

Inventors: Deyuan Xiao (Hefei, CN); Guangsu Shao (Hefei, CN); Yunsong Qiu (Hefei, CN)

Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.

H10B12/33H10B12/036H10B12/05

Abstract

Claims (39)

1. A method for manufacturing a semiconductor structure, comprising:

providing a substrate, and forming a plurality of semiconductor pillars arrayed along a first direction and a second direction on the substrate, wherein each of the semiconductor pillars comprises a first portion and a second portion on the first portion, the first direction and the second direction intersect and are both parallel to a top surface of the substrate;

forming a first supporting layer covering sidewalls and top surfaces of the second portions;

forming a first sacrificial layer covering a sidewall of each of the first portions;

filling a second sacrificial layer at least in gaps between the first sacrificial layers;

removing the first supporting layer to expose the sidewalls and the top surfaces of the second portions;

removing the first sacrificial layers, to form first filling regions surrounding the first portions, and to expose the sidewalls of the first portions:

forming a first electrode layer in each of the first filling regions;

removing the second sacrificial layer to form second filling regions surrounding the first electrode layers;

forming dielectric layers and second electrode layers sequentially in the second filling regions; and

forming a plurality of transistors, wherein channel structures of the transistors are located in the second portions, and the channel structures extend in a same direction as the second portions.

2. The method for manufacturing a semiconductor structure of claim 1 , wherein the forming a plurality of semiconductor pillars arrayed along a first direction and a second direction on the substrate, comprises:

providing a semiconductor substrate; and

forming a plurality of first trenches arranged at intervals along a first direction and a plurality of second trenches arranged at intervals along a second direction in the semiconductor substrate, wherein the first trenches divide the semiconductor substrate into a plurality of semiconductor strips, and the second trenches divide each of the semiconductor strips into a plurality of semiconductor pillars, a width of each of the semiconductor pillars in the first direction is different from a width of the semiconductor pillar in the second direction.

3. The method for manufacturing a semiconductor structure of claim 2 , further comprising:

forming third sacrificial layers at sidewalls of the first trenches prior to forming the second trenches;

enlarging a bottom of each of the first trenches;

removing the third sacrificial layers;

performing an oxidation treatment on the semiconductor strips, to completely oxidize a portion of each of the semiconductor strips, which corresponds to the enlarged portion of the first trench, into an oxide strip, and to oxidize surfaces of a remaining portion of the semiconductor strip into oxide layers; and

filling a first insulating material in gaps between the oxide layers and between the oxide strips.

4. The method for manufacturing a semiconductor structure of claim 3 , further comprising:

filling a first insulating material in the first trenches in which the third sacrificial layers are formed, after forming the third sacrificial layers on the sidewalls of the first trenches; and

forming a plurality of second supporting layers arranged at intervals in the second direction on the semiconductor strips and the first insulating material, removing the first insulating material filled in the first trenches, and enlarging the bottoms of the first trenches.

5. The method for manufacturing a semiconductor structure of claim 4 , wherein the forming the second trenches comprises:

etching the semiconductor substrate to form the second trenches by using the second supporting layers as a mask.

6. The method for manufacturing a semiconductor structure of claim 1 , wherein the forming a first supporting layer covering sidewalls and top surfaces of the second portions comprises:

filling a first insulating material between the plurality of semiconductor pillars;

removing part of the first insulating material in the first direction to form a plurality of first shallow trenches, wherein bottom surfaces of the first shallow trenches are flush with bottom surfaces of the second portions;

depositing a first supporting material on top surfaces of the semiconductor pillars and in the first shallow trenches;

removing part of the first insulating material in the second direction to form a plurality of second shallow trenches, wherein bottom surfaces of the second shallow trenches are flush with the bottom surfaces of the second portions; and

filling the first supporting material in the second shallow trenches to form the first supporting layer.

7. The method for manufacturing a semiconductor structure of claim 1 , further comprising:

alloying the first portions to reduce resistance of the first portions prior to forming a first sacrificial layer covering a sidewall of each of the first portions.

8. The method for manufacturing a semiconductor structure of claim 7 , wherein the alloying the first portions comprises:

forming a metal layer covering a sidewall of each of the first portions; and

allowing the metal layers and the first portions to react and form a metal compound by a rapid thermal process.

9. The method for manufacturing a semiconductor structure of claim 1 , wherein the forming a plurality of transistors comprises:

forming a gate structure covering at least one side of the second portion; and

forming a source and a drain respectively at two opposite ends of the second portion.

Assignments (1)

Priority Claims (1)

Continuity (2)

References Cited (62)