IP Library Granted Patent US 12,482,664
Granted Patent B2
US 12,482,664 · App. 18/105,333 · Granted Nov 25, 2025

Method of manufacturing semiconductor structure

Inventor: Hsuan-Wu Lai (Yilan, TW)
Assignee: NANYA TECHNOLOGY CORPORATION
H01L21/31116H01L21/30608
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Quick Facts
Patent No.
US 12,482,664
App. No.
18/105,333
Granted
Nov 25, 2025
Kind
B2
Abstract

A method of manufacturing a semiconductor structure is provided. The method includes providing a semiconductor wafer having a central region and a bevel region. The method also includes forming a carbon-containing layer over the central region and the bevel region of the semiconductor wafer. The method further includes performing a wet etching operation to remove the carbon-containing over the bevel region of the semiconductor wafer. The method also includes performing a baking operation on the bevel region of the semiconductor wafer.

Claims (31)

1 . A method of manufacturing a semiconductor structure, comprising:

providing a semiconductor wafer having a central region and a bevel region;

forming a carbon-containing layer over the central region and the bevel region of the semiconductor wafer;

performing a wet etching operation to remove the carbon-containing layer over the bevel region of the semiconductor wafer; and

performing a baking operation on the bevel region of the semiconductor wafer; and

forming a silicon-containing layer over the central region and the bevel region of the semiconductor wafer after performing the baking operation.

2 . The method of claim 1 , further comprising:

performing a dry etching operation on the carbon-containing layer prior to performing the wet etching operation.

3 . The method of claim 2 , wherein the carbon-containing layer over the bevel region of the semiconductor wafer is partially removed by the dry etching operation, and the carbon-containing layer over the bevel region of the semiconductor wafer is fully removed by the wet etching operation.

4 . The method of claim 1 , wherein forming the silicon-containing layer and performing the baking operation are performed in an in-situ manner.

5 . The method of claim 1 , wherein a portion of the carbon-containing layer is remained on the central region of the semiconductor wafer after performing the wet etching operation, and the silicon-containing layer is formed on the portion of the carbon-containing layer.

6 . The method of claim 1 , wherein a portion of the silicon-containing layer on the bevel region of the semiconductor wafer is free from contacting the carbon-containing layer.

7 . The method of claim 1 , wherein the baking operation is performed under a temperature equal to or greater than about 100° C. and for equal to or greater than about 90 seconds.

8 . The method of claim 7 , wherein the baking operation is performed under a temperature from about 350° C. to about 450° C.

9 . The method of claim 7 , wherein the baking operation is performed for about 90 seconds to about 150 seconds.

10 . A method of manufacturing a semiconductor structure, comprising:

providing a semiconductor wafer having a bevel region;

forming a carbon-containing layer over the bevel region of the semiconductor wafer;

performing an anisotropic etching operation on the carbon-containing layer over the bevel region of the semiconductor wafer;

performing a wet etching operation on the carbon-containing layer over the bevel region of the semiconductor wafer; and

performing a baking operation on the bevel region of the semiconductor wafer.

11 . The method of claim 10 , wherein the wet etching operation is performed after the anisotropic etching operation.

12 . The method of claim 10 , wherein the baking operation is performed under a temperature equal to or greater than about 100° C. and for about 90 seconds to about 150 seconds.

13 . The method of claim 12 , wherein the baking operation is performed under a temperature from about 350° C. to about 450° C.

14 . The method of claim 10 , further comprising:

forming a silicon-containing layer on the semiconductor wafer after performing the baking operation.

15 . The method of claim 14 , wherein forming the silicon-containing layer and performing the baking operation are performed in an in-situ manner.

16 . The method of claim 14 , wherein a temperature for forming the silicon-containing layer and a temperature for performing the baking operation are substantially the same.

17 . The method of claim 14 , wherein the silicon-containing layer is formed on a portion of the carbon-containing layer on a region distinct from the bevel region of the semiconductor wafer.

18 . The method of claim 17 , wherein the silicon-containing layer comprises amorphous silicon.

19 . The method of claim 17 , wherein the carbon-containing layer comprises diamond-like carbon.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 3, 2023
From: LAI, HSUAN-WU
To: NANYA TECHNOLOGY CORPORATION
Reel/Frame 062582/0054 →
Continuity (1)
Related Publication 20240266183A1 · Aug 8, 2024
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