Structure and formation method of semiconductor device structure
Structures and formation methods of a semiconductor device structure are provided. The semiconductor device structure includes a gate stack over a semiconductor substrate and a cap element over the gate stack. The cap element has an upper portion and a lower portion, and the upper portion is wider than the lower portion. The semiconductor device structure also includes a spacer element over a sidewall of the cap element and a sidewall of the gate stack.
1 . A method, comprising:
forming a gate structure over a semiconductor substrate;
forming a first spacer element and a second spacer element on opposing sides of the gate structure;
removing the gate structure to form a first recess, wherein after removing the gate structure, upper sidewalls of the first spacer element and the second spacer element have tapered upper sidewalls facing the first recess, the tapered upper sidewalls tapering away from each other;
after removing the gate structure, forming a first dielectric layer in the first recess and a metal gate stack over the first dielectric layer in the first recess;
etching back the metal gate stack to form a second recess between the first spacer element and the second spacer element, a bottom of the second recess being below the tapered upper sidewalls, wherein after etching an upper surface of the metal gate stack is below a bottom of the tapered upper sidewalls, wherein after etching the upper surface of the metal gate stack is above an upper surface of the first dielectric layer; and
forming a cap element above the metal gate stack and in the second recess between the first spacer element and the second spacer element, wherein the cap element comprises a dielectric material in physical contact with the metal gate stack, and wherein a bottom surface of the cap element is below the tapered upper sidewalls.
2 . The method of claim 1 , wherein removing the gate structure comprises:
performing a first etch process to recess the gate structure below an upper surface of the first spacer element and the second spacer element;
performing a second etch process to further recess the gate structure and to laterally etch the first spacer element and the second spacer element; and
performing a third etch process to remove remaining portions of the gate structure.
3 . The method of claim 2 , wherein the second etch process etches the first spacer element and the second spacer element at a higher rate relative to the gate structure than the first etch process and the third etch process.
4 . The method of claim 1 , wherein forming the metal gate stack comprises forming a work function layer and a conductive fill over the work function layer, wherein etching back the metal gate stack comprises recessing the work function layer more than the conductive fill.
5 . The method of claim 4 , wherein the cap element contacts a sidewall of the conductive fill.
6 . The method of claim 1 , wherein the gate structure comprises a polysilicon material layer.
7 . The method of claim 6 , wherein the gate structure comprises a dummy gate dielectric.
8 . A method, comprising:
forming a gate structure over a semiconductor substrate;
forming a first spacer element on a first sidewall of the gate structure;
forming a second spacer element on a second sidewall of the gate structure, the second sidewall of the gate structure being opposite to the first sidewall of the gate structure;
removing the gate structure to form a first recess between the first spacer element and the second spacer element, wherein the first recess becomes narrower as the first recess extends toward the semiconductor substrate for a first distance;
forming a dielectric layer along a bottom and sidewalls of the first recess;
depositing a conductive material over the dielectric layer, the conductive material filling the first recess;
recessing the dielectric layer and the conductive material to form a second recess between the first spacer element and the second spacer element, a topmost surface of the conductive material being above a topmost surface of the dielectric layer after the recessing, wherein the topmost surface of the conductive material is a second distance below an upper surface of the first spacer element, the second distance being greater than the first distance; and
forming a cap element in the second recess.
9 . The method of claim 8 , further comprising depositing a conductive layer over the dielectric layer in the first recess, wherein depositing the conductive material comprises depositing the conductive material over the conductive layer, wherein recessing the dielectric layer and the conductive material further comprises recessing the conductive layer.
10 . The method of claim 9 , wherein the conductive material extends above an upper surface of the conductive layer.
11 . The method of claim 9 , wherein the cap element contacts a sidewall of the conductive material.
12 . The method of claim 8 , wherein removing the gate structure comprises performing a plurality of different etch processes.
13 . The method of claim 12 , wherein the plurality of different etch processes comprises:
a first etch process to partially remove the gate structure; and
a second etch process to further recess the gate structure and to laterally etch the first spacer element and the second spacer element.
14 . The method of claim 8 , wherein an upper surface of the cap element is level with an upper surface of the first spacer element.
15 . A method, comprising:
forming a gate structure over an active region;
forming a first spacer element on a first sidewall of the gate structure;
forming a second spacer element on a second sidewall of the gate structure, the gate structure being between the first spacer element and the second spacer element, the first spacer element having a first sidewall facing the second spacer element, the second spacer element having a first sidewall facing the first spacer element;
removing the gate structure, an upper portion of the first spacer element, and an upper portion of the second spacer element, removing the gate structure forming a first tapered portion of the first sidewall of the first spacer element and a second tapered portion of the first sidewall of the second spacer element, wherein removing the gate structure, the upper portion of the first spacer element, and the upper portion of the second spacer element comprises:
performing a first etch process to partially remove the gate structure; and
after performing the first etch process, performing a second etch process to remove at least a portion of the gate structure, wherein the second etch process etches the first spacer element and the second spacer element at a greater rate relative to the gate structure than the first etch process;
after removing the gate structure, forming a first dielectric layer over the active region and one or more conductive layers over the first dielectric layer, wherein an uppermost surface of the one or more conductive layers is below an uppermost surface of the first spacer element in a cross-sectional view, wherein the first dielectric layer extends between the one or more conductive layers and the first spacer element and between the one or more conductive layers and the second spacer element, wherein an uppermost surface of the first dielectric layer is below the uppermost surface of the first spacer element in the cross-sectional view; and
forming a second dielectric layer over the first dielectric layer and the one or more conductive layers between the first spacer element and the second spacer element.
16 . The method of claim 15 , further comprising:
after performing the second etch process, performing a third etch process to remove remaining portions of the gate structure.
17 . The method of claim 16 , wherein the second etch process etches the first spacer element and the second spacer element at a greater rate relative to the gate structure than the third etch process.
18 . The method of claim 17 , wherein the one or more conductive layers comprise a first conductive layer and a second conductive layer over the first conductive layer, wherein the first conductive layer extends between the second conductive layer and the first spacer element, wherein the first conductive layer is recessed below an upper surface of the second conductive layer along the first sidewall of the first spacer element.
19 . The method of claim 18 , wherein an upper surface of the first conductive layer adjacent the first sidewall of the first spacer element is below the first tapered portion of the first spacer element.
20 . The method of claim 15 , wherein an upper surface of the one or more conductive layers is above an upper surface of the first dielectric layer.